############################################################################################
## 
## DSP Builder (Version 7.0)
## Quartus II development tool and MATLAB/Simulink Interface
## 
## Legal Notice: ?2001 Altera Corporation. All rights reserved.  Your use of Altera  
## Corporation's design tools, logic functions and other software and tools, and its  
## AMPP partner logic functions, and any output files any of the foregoing            
## (including device programming or simulation files), and any associated             
## documentation or information are expressly subject to the terms and conditions     
## of the Altera Program License Subscription Agreement, Altera MegaCore Function     
## License Agreement, or other applicable license agreement, including, without       
## limitation, that your use is for the sole purpose of programming logic devices     
## manufactured by Altera and sold by Altera or its authorized distributors.          
## Please refer to the applicable agreement for further details.                      
##
##
############################################################################################

# TCL Script for Quartus II 

# Packages
package require ::quartus::project
package require ::quartus::flow

# Directory Variables 
set workdir "."
set libdir "e:/altera/70/DSPBuilder/Altlib"
set megadir "e:/altera/70/dspbuilder/megacorelib"


# Change to working directory 
cd $workdir

# Create Quartus II project 
project_new dds_top -overwrite
set_global_assignment -name "VHDL_FILE" "$libdir/DSPBUILDERPACK.VHD"
set_global_assignment -name "VHDL_FILE" "$libdir/DSPBUILDER.VHD"
set_global_assignment -name "VHDL_FILE" "$workdir/DDS.vhd";
set_global_assignment -name "VHDL_FILE" "$workdir/dds_top.vhd";
set_global_assignment -name "SIMULATOR_SETTINGS" "dds_top"
set_global_assignment -name "COMPILER_SETTINGS" "dds_top"
set_global_assignment -name "USER_LIBRARIES" ";$megadir"

# Set Compiler assignements 
set_global_assignment -name "FAMILY" "stratix";
set_global_assignment -name "APEX20K_OPTIMIZATION_TECHNIQUE" "AREA"
set_global_assignment -name "MERCURY_OPTIMIZATION_TECHNIQUE" "AREA"
set_global_assignment -name "FLEX10K_OPTIMIZATION_TECHNIQUE" "AREA"
set_global_assignment -name "FLEX6K_OPTIMIZATION_TECHNIQUE" "AREA"
set_global_assignment -name "STRATIX_OPTIMIZATION_TECHNIQUE" "BALANCED"
set_global_assignment -name "STRATIXII_OPTIMIZATION_TECHNIQUE" "BALANCED"
set_global_assignment -name "CYCLONE_OPTIMIZATION_TECHNIQUE" "BALANCED"
set_global_assignment -name "CYCLONEII_OPTIMIZATION_TECHNIQUE" "BALANCED"
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name FMAX_REQUIREMENT "20 ns"
set_global_assignment -name "DEVICE" "AUTO";

# Simulator Assignments for test
set_project_settings  -sim "dds_top"
set_global_assignment -name "USE_COMPILER_SETTINGS" "dds_top"
set_global_assignment -name "VECTOR_INPUT_SOURCE" "dds_top.vec"

project_close


# Project compilation section
set CompilationType  [lindex $quartus(args) 0]
set MapCompileOk 0
set FitCompileOk 0

project_open dds_top
if {$CompilationType==1} {
	if { [catch { execute_module -tool map } result] }  {
			set MapCompileOk 0 
			puts "ERROR: Analysis & Synthesis failed. See the report file."
		} else {
			set MapCompileOk 1 
			puts "INFO: Analysis & Synthesis was successful."
		}
} elseif {$CompilationType==2} {
	if { [catch { execute_flow -compile } result] }  {
			set FitCompileOk 0 
			puts "ERROR: Compilation failed. See report files"
		} else {
			set FitCompileOk 1 
			puts "INFO: Compilation was successful"
		}
}