?? cymometer.rpt
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Project Information g:\eda_2\cymometer\cymometer.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/03/2007 20:50:47
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was unsuccessful
CYMOMETER
** DEVICE SUMMARY **
Chip/ Input Output Bidir LCs
POF Device Pins Pins Pins LCs % Utilized
cymometer
EPF8282ALC84-4 2 16 0 256 No Fit
User Pins: 2 16 0
Project Information g:\eda_2\cymometer\cymometer.rpt
** PROJECT COMPILATION MESSAGES **
Error: Project does not fit in specified device(s)
Error: No fit found, generating Report File
(See individual chip error summaries for additional information)
Project Information g:\eda_2\cymometer\cymometer.rpt
** FILE HIERARCHY **
|lpm_add_sub:374|
|lpm_add_sub:374|addcore:adder|
|lpm_add_sub:374|altshift:result_ext_latency_ffs|
|lpm_add_sub:374|altshift:carry_ext_latency_ffs|
|lpm_add_sub:374|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1086|
|lpm_add_sub:1086|addcore:adder|
|lpm_add_sub:1086|altshift:result_ext_latency_ffs|
|lpm_add_sub:1086|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1086|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1145|
|lpm_add_sub:1145|addcore:adder|
|lpm_add_sub:1145|altshift:result_ext_latency_ffs|
|lpm_add_sub:1145|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1145|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1232|
|lpm_add_sub:1232|addcore:adder|
|lpm_add_sub:1232|altshift:result_ext_latency_ffs|
|lpm_add_sub:1232|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1232|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1347|
|lpm_add_sub:1347|addcore:adder|
|lpm_add_sub:1347|altshift:result_ext_latency_ffs|
|lpm_add_sub:1347|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1347|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1490|
|lpm_add_sub:1490|addcore:adder|
|lpm_add_sub:1490|altshift:result_ext_latency_ffs|
|lpm_add_sub:1490|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1490|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1661|
|lpm_add_sub:1661|addcore:adder|
|lpm_add_sub:1661|altshift:result_ext_latency_ffs|
|lpm_add_sub:1661|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1661|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1860|
|lpm_add_sub:1860|addcore:adder|
|lpm_add_sub:1860|altshift:result_ext_latency_ffs|
|lpm_add_sub:1860|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1860|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2087|
|lpm_add_sub:2087|addcore:adder|
|lpm_add_sub:2087|altshift:result_ext_latency_ffs|
|lpm_add_sub:2087|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2087|altshift:oflow_ext_latency_ffs|
Device-Specific Information: g:\eda_2\cymometer\cymometer.rpt
cymometer
***** Logic for device 'cymometer' contains errors -- see ERROR SUMMARY.
Device: EPF8282ALC84-4
FLEX 8000 Configuration Scheme: Active Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable DCLK Output in User Mode = OFF
Disable Start-Up Time-Out = OFF
Enable JTAG Support = OFF
Device-Specific Information: g:\eda_2\cymometer\cymometer.rpt
cymometer
** ERROR SUMMARY **
Error: Project requires too many (256/208) logic cells
Device-Specific Information: g:\eda_2\cymometer\cymometer.rpt
cymometer
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 0/64 ( 0%)
Total logic cells used: 0/208 ( 0%)
Average fan-in: 3.38/4 ( 84%)
Total fan-in: 866/832 (104%)
Total input pins required: 2
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 2
Total logic cells required: 256
Total flipflops required: 90
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Synthesized logic cells: 70/ 208 ( 33%)
Logic Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 Total
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Device-Specific Information: g:\eda_2\cymometer\cymometer.rpt
cymometer
** INPUTS **
Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
12 - - -- INPUT G 0 0 0 0 clkin
31 - - -- INPUT G 0 0 0 0 sysclk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\eda_2\cymometer\cymometer.rpt
cymometer
** OUTPUTS **
Fed By Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
?? - ? ? OUTPUT 0 1 0 0 scan0
?? - ? ? OUTPUT 0 1 0 0 scan1
?? - ? ? OUTPUT 0 1 0 0 scan2
?? - ? ? OUTPUT 0 1 0 0 scan3
?? - ? ? OUTPUT 0 1 0 0 scan4
?? - ? ? OUTPUT 0 1 0 0 scan5
?? - ? ? OUTPUT 0 1 0 0 scan6
?? - ? ? OUTPUT 0 1 0 0 scan7
?? - ? ? OUTPUT 0 1 0 0 seg70
?? - ? ? OUTPUT 0 1 0 0 seg71
?? - ? ? OUTPUT 0 1 0 0 seg72
?? - ? ? OUTPUT 0 1 0 0 seg73
?? - ? ? OUTPUT 0 1 0 0 seg74
?? - ? ? OUTPUT 0 1 0 0 seg75
?? - ? ? OUTPUT 0 1 0 0 seg76
?? - ? ? OUTPUT 0 1 0 0 seg77
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\eda_2\cymometer\cymometer.rpt
cymometer
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC Row Col Primitive Code INP FBK OUT FBK Name
- ?? ? ? AND2 0 2 0 3 |LPM_ADD_SUB:374|addcore:adder|:139
- ?? ? ? AND2 0 3 0 4 |LPM_ADD_SUB:374|addcore:adder|:147
- ?? ? ? AND2 0 2 0 1 |LPM_ADD_SUB:374|addcore:adder|:151
- ?? ? ? AND2 0 4 0 3 |LPM_ADD_SUB:374|addcore:adder|:159
- ?? ? ? AND2 0 2 0 3 |LPM_ADD_SUB:374|addcore:adder|:163
- ?? ? ? AND2 0 3 0 3 |LPM_ADD_SUB:374|addcore:adder|:171
- ?? ? ? AND2 0 3 0 3 |LPM_ADD_SUB:374|addcore:adder|:179
- ?? ? ? AND2 0 3 0 3 |LPM_ADD_SUB:374|addcore:adder|:187
- ?? ? ? AND2 0 3 0 3 |LPM_ADD_SUB:374|addcore:adder|:195
- ?? ? ? AND2 0 3 0 3 |LPM_ADD_SUB:374|addcore:adder|:203
- ?? ? ? AND2 0 3 0 3 |LPM_ADD_SUB:374|addcore:adder|:211
- ?? ? ? AND2 0 3 0 3 |LPM_ADD_SUB:374|addcore:adder|:219
- ?? ? ? AND2 0 2 0 1 |LPM_ADD_SUB:374|addcore:adder|:223
- ?? ? ? AND2 s 0 2 0 1 |LPM_ADD_SUB:1086|addcore:adder|~55~1
- ?? ? ? AND2 0 2 0 4 |LPM_ADD_SUB:1086|addcore:adder|:55
- ?? ? ? OR2 ! 0 2 0 4 |LPM_ADD_SUB:1145|addcore:adder|:55
- ?? ? ? OR2 ! 0 2 0 4 |LPM_ADD_SUB:1347|addcore:adder|:55
- ?? ? ? AND2 0 2 0 1 |LPM_ADD_SUB:1490|addcore:adder|:55
- ?? ? ? AND2 0 2 0 1 |LPM_ADD_SUB:1661|addcore:adder|:55
- ?? ? ? AND2 0 3 0 1 |LPM_ADD_SUB:1661|addcore:adder|:59
- ?? ? ? AND2 0 2 0 1 |LPM_ADD_SUB:1860|addcore:adder|:55
- ?? ? ? AND2 0 2 0 1 |LPM_ADD_SUB:2087|addcore:adder|:55
- ?? ? ? DFF + 0 3 0 1 cnt24 (:19)
- ?? ? ? DFF + 0 3 0 2 cnt23 (:20)
- ?? ? ? DFF + 0 2 0 3 cnt22 (:21)
- ?? ? ? DFF + 0 3 0 2 cnt21 (:22)
- ?? ? ? DFF + 0 2 0 3 cnt20 (:23)
- ?? ? ? DFF + 0 3 0 2 cnt19 (:24)
- ?? ? ? DFF + 0 2 0 3 cnt18 (:25)
- ?? ? ? DFF + 0 3 0 2 cnt17 (:26)
- ?? ? ? DFF + 0 2 0 3 cnt16 (:27)
- ?? ? ? DFF + 0 3 0 2 cnt15 (:28)
- ?? ? ? DFF + 0 2 0 3 cnt14 (:29)
- ?? ? ? DFF + 0 3 0 2 cnt13 (:30)
- ?? ? ? DFF + 0 2 0 3 cnt12 (:31)
- ?? ? ? DFF + 0 3 0 2 cnt11 (:32)
- ?? ? ? DFF + 0 2 0 3 cnt10 (:33)
- ?? ? ? DFF + 0 3 0 2 cnt9 (:34)
- ?? ? ? DFF + 0 3 0 3 cnt8 (:35)
- ?? ? ? DFF + 0 2 0 2 cnt7 (:36)
- ?? ? ? DFF + 0 3 0 1 cnt6 (:37)
- ?? ? ? DFF + 0 3 0 10 cnt5 (:38)
- ?? ? ? DFF + 0 2 0 11 cnt4 (:39)
- ?? ? ? DFF + 0 3 0 9 cnt3 (:40)
- ?? ? ? DFF + 0 2 0 2 cnt2 (:41)
- ?? ? ? DFF + 0 2 0 1 cnt1 (:42)
- ?? ? ? DFF + 0 0 0 2 cnt0 (:43)
- ?? ? ? DFF + 0 1 0 64 clk_cnt (:44)
- ?? ? ? DFF + 0 3 0 3 cntp13 (:45)
- ?? ? ? DFF + 0 3 0 4 cntp12 (:46)
- ?? ? ? DFF + 0 3 0 5 cntp11 (:47)
- ?? ? ? DFF + 0 1 0 6 cntp10 (:48)
- ?? ? ? DFF + 0 3 0 4 cntp23 (:49)
- ?? ? ? DFF + 0 3 0 5 cntp22 (:50)
- ?? ? ? DFF + 0 3 0 6 cntp21 (:51)
- ?? ? ? DFF + 0 2 0 6 cntp20 (:52)
- ?? ? ? DFF + 0 3 0 4 cntp33 (:53)
- ?? ? ? DFF + 0 3 0 5 cntp32 (:54)
- ?? ? ? DFF + 0 3 0 6 cntp31 (:55)
- ?? ? ? DFF + 0 3 0 6 cntp30 (:56)
- ?? ? ? DFF + 0 3 0 5 cntp43 (:57)
- ?? ? ? DFF + 0 3 0 5 cntp42 (:58)
- ?? ? ? DFF + 0 3 0 7 cntp41 (:59)
- ?? ? ? DFF + 0 2 0 8 cntp40 (:60)
- ?? ? ? DFF + 0 3 0 4 cntp53 (:61)
- ?? ? ? DFF + 0 3 0 5 cntp52 (:62)
- ?? ? ? DFF + 0 3 0 5 cntp51 (:63)
- ?? ? ? DFF + 0 2 0 6 cntp50 (:64)
- ?? ? ? DFF + 0 3 0 4 cntp63 (:65)
- ?? ? ? DFF + 0 3 0 4 cntp62 (:66)
- ?? ? ? DFF + 0 3 0 7 cntp61 (:67)
- ?? ? ? DFF + 0 2 0 8 cntp60 (:68)
- ?? ? ? DFF + 0 3 0 4 cntp73 (:69)
- ?? ? ? DFF + 0 3 0 5 cntp72 (:70)
- ?? ? ? DFF + 0 3 0 5 cntp71 (:71)
- ?? ? ? DFF + 0 2 0 6 cntp70 (:72)
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