library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lifo is
port(clr:in std_logic;--------清零信號
     push:in std_logic;-------壓棧信號
     pop:in std_logic;--------出棧信號
     clk:in std_logic;--------時鐘信號
     din:in std_logic_vector(7 downto 0);------數據輸入端
     empty:out std_logic;-----棧空信號
     full:out std_logic;------棧滿信號
     dout:out std_logic_vector(7 downto 0));---數據輸出端
end;
architecture one of lifo is
	type memory is array(0 to 8)of std_logic_vector(7 downto 0);----存儲空間
begin
process(clk,clr)
	variable stack:memory;
	variable cnt:integer range 0 to 8;----設置指針，棧底指針為0
begin
if clr='1' then----------------------------------清零
        dout<=(others=>'0');
        full<='0';
        cnt:=0;
elsif clk'event and clk='1' then     
	if push='1' and pop='0' and cnt/=8 then-----------壓棧
		empty<='0';
		stack(cnt):=din;--------------------存入數據
		cnt:=cnt+1;-------------------------指針加1
	elsif pop='1' and push='0' and cnt/=0 then---------出棧
		full<='0';
		cnt:=cnt-1;-------------------------指針減1
	    dout<=stack(cnt);-------------------輸出數據
	elsif cnt=0 then
		empty<='1';
		dout<=(others=>'0');
	elsif cnt=8 then
		full<='1';
	end if;
end if;
end process;
end;