; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; RS.vhd                           ; yes             ; User VHDL File  ; D:/my_eda/RS/RS.vhd          ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 2     ;
;                                             ;       ;
; Total combinational functions               ; 2     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 1     ;
;     -- <=2 input functions                  ; 1     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 2     ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
;     -- Dedicated logic registers            ; 0     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 4     ;
; Maximum fan-out node                        ; q1~0  ;
; Maximum fan-out                             ; 3     ;
; Total fan-out                               ; 7     ;
; Average fan-out                             ; 1.17  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |RS                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 4    ; 0            ; |RS                 ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops               ;
+--------------------------------------------------------+---+
; Logic Cell Name                                        ;   ;
+--------------------------------------------------------+---+
; q~0                                                    ;   ;
; Number of logic cells representing combinational loops ; 1 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu May 31 20:51:26 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RS -c RS
Info: Found 2 design units, including 1 entities, in source file RS.vhd
    Info: Found design unit 1: RS-one
    Info: Found entity 1: RS
Warning: Can't analyze file -- file D:/my_eda/RS/RS.bdf is missing
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Found 1 design units, including 1 entities, in source file RS_1.bdf
    Info: Found entity 1: RS_1
Info: Elaborating entity "RS" for the top level hierarchy
Info: Implemented 6 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 2 output pins
    Info: Implemented 2 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 135 megabytes of memory during processing
    Info: Processing ended: Thu May 31 20:51:31 2007
    Info: Elapsed time: 00:00:05