?? ssx31bdrv.c
字號:
#ifdef __cplusplus
extern "C" {
#endif
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/delay.h>
/* #include <asm/io.h> */
#include "../def.h"
#include "../SSX31.h"
#include "SSX31BDrv.h"
MBufQ_S mbufq[SSX31B_MBUFQ_LEN];
USHORT mbufq_writer;
USHORT mbufq_reader;
//extern int ssx31_dma_virt_mapping_add(ULONG dma_phys_addr,ULONG virtAddr,ULONG BufLen);
//extern void ssx31_dma_virt_mapping_del(ULONG dma_phys_addr, ULONG virtAddr);
extern ULONG ssx31_dma_virt_mapping_findByDmaPhys(ULONG dma_phys_addr,ULONG* BufLen);
extern ULONG ssx31_dma_virt_mapping_findByVirt(ULONG virtAddr,ULONG* BufLen);
extern void* ssx31_consistent_alloc(int flag, ULONG size, dma_addr_t* pDmaAddr);
extern void ssx31_consistent_free(void* virtAddr,ULONG size, dma_addr_t dmaAddr);
extern ULONG ssx31_dma_virt_mapping_PreDelByDmaPhys(ULONG dma_phys_addr,ULONG* BufLen);
extern ULONG ssx31_dma_virt_mapping_PreDelByVirt(ULONG virtAddr,ULONG* BufLen);
ULONG SSX31B_Vrp_IoCtl(ULONG ulPhyLink, ULONG ulCmdIndex, CHAR *pData);
ULONG SSX31B_Transmit(ULONG , MBUF_S *, UCHAR* , dma_addr_t , ULONG );
ULONG SSX31B_Transmit_Basic(ULONG , MBUF_S *, UCHAR* , dma_addr_t , ULONG );
VOID SSX31B_ISR(SSX31BDRV_CTRL * pDrvCtrl);
ULONG SSX31B_PhyUpdateSA(ULONG ulPhyLink, VOID * pTDB, dma_addr_t pTDB_dma_phys, ULONG ulSaNum);
VOID SSX31B_ShowReg(SSX31BDRV_CTRL * pDrvCtrl, UCHAR* pucBuffer);
ULONG SSX31B_FreeBDDesc(SSX31BDRV_CTRL * pDrvCtrl, SSX31B_IPSEC_RD* pRdDesc);
ULONG four_bytes_align_en (ULONG ulBusAddr,ULONG ulVirAddr);
extern wait_queue_head_t appwait;
extern wait_queue_head_t inwait;
char bIPSecPerf;
extern unsigned long g_ipsec_performace_num;
extern struct semaphore ipsec_perf_sema;
ULONG SSX31B_Reset(SSX31BDRV_CTRL* pDrvCtrl)
{
ULONG ulTempID = 0x10;
LONG lIntmask = 0;
SplImp(&lIntmask);
PciWrite32(SSX31B_REG_MRID, ulTempID | MASK_MRID_RST);
UsDelay(10);
ulTempID &= ~MASK_MRID_RST;
PciWrite32(SSX31B_REG_MRID, ulTempID);
PciRead32(SSX31B_REG_MRID, &ulTempID);
if ((ulTempID & 0xff) != 0x10)
{
PRINT("SSX31B version err2:%08x.\r\n", ulTempID);
return ERR;
}
SplX(lIntmask);
return OK;
}
ULONG SSX31B_PCInit(SSX31BDRV_CTRL* pDrvCtrl)
{
pci_write_config_dword (pDrvCtrl->pPciDev, 0x04, 0xFFFF0146 );
pci_write_config_word (pDrvCtrl->pPciDev, 0x0c, 0x4020 );
return OK;
}
ULONG SSX31B_SdramInit(SSX31BDRV_CTRL* pDrvCtrl)
{
ULONG ulTemp, ulTemp1;
PciWrite32(SSX31B_REG_CLK_ENABLE, CLOCK_ENABLE);
ulTemp = SDRAM_CTRL_COL_BIT;
ulTemp <<= 3;
ulTemp |= SDRAM_CTRL_CAS_LATENCY;
ulTemp <<= 16;
ulTemp |= SDRAM_CTRL_REFRESH_FREQ;
ulTemp |= SDRAM_CTRL_SDR_INIT;
PciWrite32(SSX31B_REG_SDRAM_CTRL, ulTemp);
PciRead32(SSX31B_REG_SDRAM_CTRL, &ulTemp1);
if (ulTemp1 != ulTemp)
{
PRINT("\r\nSSX31B SDRAM init err 1 write %08x read %08x \r\n", ulTemp, ulTemp1);
return ERR;
}
ulTemp &= ~SDRAM_CTRL_SDR_INIT;
PciWrite32(SSX31B_REG_SDRAM_CTRL, ulTemp);
PciRead32(SSX31B_REG_SDRAM_CTRL, &ulTemp1);
if (ulTemp1 != ulTemp)
{
PRINT("\r\nSSX31B SDRAM init err 2 write %08x read %08x \r\n", ulTemp, ulTemp1);
return ERR;
}
PRINT("\r\nSSX31B SDRAM Init %08x done!\n", ulTemp);
return OK;
}
ULONG SSX31B_MCInit(SSX31BDRV_CTRL* pDrvCtrl)
{
ULONG ulTmp;
if (SSX31B_Reset(pDrvCtrl) == ERR)
goto InitError;
if (SSX31B_SdramInit(pDrvCtrl) == ERR)
goto InitError;
ulTmp = (INT_CTRL2_PAKT_COUNT << INT_CTRL2_TIME_COUNT_BIT);
ulTmp |= INT_CTRL2_TIME_INTERVAL;
PciWrite32(SSX31B_REG_INT_CTRL2, ulTmp);
PciWrite32(SSX31B_REG_INT_CTRL1, ulTmp);
PciWrite32(SSX31B_REG_INT_MASK, SSX31B_INT_MASK | INT_MASK_DMA2_PAKT_OPDONE | INT_MASK_DMA2_PROC_TMOUT);
PciWrite32(SSX31B_REG_CYC_CNT_1US, CYC_CNT_1US);
return OK;
InitError:
return ERR;
}
ULONG SSX31B_PEInit(SSX31BDRV_CTRL* pDrvCtrl)
{
ULONG ulTmp;
ulTmp = (PE_CTRL_ENGINE_SEL << PE_CTRL_ENGINE_SEL_BIT); /* three engine */
ulTmp |= PE_CTRL_PACK_FILTER;
PciWrite32(SSX31B_REG_PE_CTRL, ulTmp);
return OK;
}
ULONG SSX31B_MemoryInit(SSX31BDRV_CTRL* pDrvCtrl)
{
ULONG ulIPSecMemPoolSize, ulSaMemPoolSize, ulPkeMemPoolSize, i,ulSize,ulGatherSize,ulCtrlWordSize;
dma_addr_t dma_buf_phys;
pDrvCtrl->ulIPSecBDDescs = SSX31B_IPSEC_BDQUEUE_LEN;
pDrvCtrl->ulIPSecRDDescs = SSX31B_IPSEC_RDQUEUE_LEN;
ulIPSecMemPoolSize = pDrvCtrl->ulIPSecBDDescs * (SSX31B_IPSEC_BD_LENGTH) + \
pDrvCtrl->ulIPSecRDDescs * (SSX31B_IPSEC_RD_LENGTH);
pDrvCtrl->ulSaBDDescs = SSX31B_SA_BDQUEUE_LEN;
pDrvCtrl->ulSaRDDescs = SSX31B_SA_RDQUEUE_LEN;
ulSaMemPoolSize = pDrvCtrl->ulSaBDDescs * (SSX31B_BASIC_BD_LENGTH) + \
pDrvCtrl->ulSaRDDescs * (SSX31B_BASIC_RD_LENGTH);
pDrvCtrl->ulPkeBDDescs = SSX31B_PKE_BDQUEUE_LEN;
pDrvCtrl->ulPkeRDDescs = SSX31B_PKE_RDQUEUE_LEN;
ulPkeMemPoolSize = pDrvCtrl->ulPkeBDDescs * (SSX31B_PKE_BD_LENGTH) + \
pDrvCtrl->ulPkeRDDescs * (SSX31B_PKE_RD_LENGTH);
ulSize= ulIPSecMemPoolSize + ulSaMemPoolSize + ulPkeMemPoolSize;
pDrvCtrl->ulMemBase = (ULONG) consistent_alloc(GFP_KERNEL|GFP_DMA,ulSize,&dma_buf_phys);
if (pDrvCtrl->ulMemBase == 0)
{
PRINT("\r\nSSX31B mem Init failed.");
return ERR;
}
pDrvCtrl->ulMemSize=ulSize;
pDrvCtrl->ulMemBase_dmaaddr=dma_buf_phys;
/*toyinfo*/
#ifdef HI_DBG
PRINT("(IPSec,Sa,Pke) MemPool allocated:%ld Bytes (%ld+%ld+%ld)\n",ulSize,ulIPSecMemPoolSize,ulSaMemPoolSize,ulPkeMemPoolSize);
#endif
Mem_Set((VOID*)pDrvCtrl->ulMemBase, 0, ulSize);
ulGatherSize = pDrvCtrl->ulIPSecBDDescs * SSX31B_ICD_LENGTH * SSX31B_MAX_GATHER;
pDrvCtrl->pstGather = (SSX31B_ICD* )consistent_alloc(GFP_KERNEL|GFP_DMA,ulGatherSize,&dma_buf_phys);
if (pDrvCtrl->pstGather == NULL)
{
consistent_free((void *)(pDrvCtrl->ulMemBase),ulSize,(dma_addr_t)(pDrvCtrl->ulMemBase_dmaaddr));
PRINT("\r\nSSX31B Init ICD failed.");
return 1;
}
pDrvCtrl->ulGatherSize=ulGatherSize;
pDrvCtrl->pstGather_dmaaddr=(SSX31B_ICD*)dma_buf_phys;
/*toyinfo*/
#ifdef HI_DBG
PRINT("IPSecICD MemPool Mem allocated:%ld Bytes\n",ulGatherSize);
#endif
Mem_Set((VOID*)pDrvCtrl->pstGather, 0, ulGatherSize);
ulCtrlWordSize= pDrvCtrl->ulIPSecBDDescs * SSX31B_PE_HEADER_LEHGTN;
pDrvCtrl->ulCtrlWordMemBase = (ULONG)consistent_alloc(GFP_KERNEL|GFP_DMA,ulCtrlWordSize,&dma_buf_phys);
if (pDrvCtrl->ulCtrlWordMemBase == 0)
{
consistent_free((void *)(pDrvCtrl->ulMemBase),ulSize,(dma_addr_t)(pDrvCtrl->ulMemBase_dmaaddr));
consistent_free((void *)(pDrvCtrl->pstGather),ulGatherSize,(dma_addr_t)(pDrvCtrl->pstGather_dmaaddr));
PRINT("\r\nSSX31B Init ICD CtrlWord failed.");
return 1;
}
pDrvCtrl->ulCtrlWordSize=ulCtrlWordSize;
pDrvCtrl->ulCtrlWordMemBase_dmaaddr=dma_buf_phys;
/*toyinfo*/
#ifdef HI_DBG
PRINT("IPSecCtrlWord MemPool Mem allocated:%ld Bytes\n",ulCtrlWordSize);
#endif
Mem_Set((VOID*)pDrvCtrl->ulCtrlWordMemBase, 0, ulCtrlWordSize);
pDrvCtrl->ulIPSecBDMemBase = pDrvCtrl->ulMemBase;
pDrvCtrl->ulIPSecBDMemBase_dmaaddr=pDrvCtrl->ulMemBase_dmaaddr;
pDrvCtrl->ulFreeIPSecBDs = pDrvCtrl->ulIPSecBDDescs;
pDrvCtrl->ulCurrIPSecBdReadPtr = 0;
pDrvCtrl->ulCurrIPSecBdWritePtr = 0;
pDrvCtrl->ulIPSecRDMemBase = pDrvCtrl->ulIPSecBDMemBase + pDrvCtrl->ulIPSecBDDescs * (SSX31B_IPSEC_BD_LENGTH);
pDrvCtrl->ulIPSecRDMemBase_dmaaddr= SSX31DRV_VIRT2DMA((pDrvCtrl->ulIPSecRDMemBase), (pDrvCtrl->ulMemBase),(pDrvCtrl->ulMemBase_dmaaddr));
pDrvCtrl->ulFreeIPSecRDs = pDrvCtrl->ulIPSecRDDescs;
pDrvCtrl->ulCurrIPSecRdReadPtr = 0;
pDrvCtrl->ulCurrIPSecRdWritePtr = 0;
pDrvCtrl->ulSaBDMemBase = pDrvCtrl->ulMemBase + ulIPSecMemPoolSize;
pDrvCtrl->ulSaBDMemBase_dmaaddr= pDrvCtrl->ulMemBase_dmaaddr+ ulIPSecMemPoolSize;
pDrvCtrl->ulFreeSaBDs = pDrvCtrl->ulSaBDDescs;
pDrvCtrl->ulCurrSaBdReadPtr = 0;
pDrvCtrl->ulCurrSaBdWritePtr = 0;
pDrvCtrl->ulSaRDMemBase = pDrvCtrl->ulSaBDMemBase + pDrvCtrl->ulSaBDDescs * (SSX31B_BASIC_BD_LENGTH);
pDrvCtrl->ulSaRDMemBase_dmaaddr= SSX31DRV_VIRT2DMA(pDrvCtrl->ulSaRDMemBase, pDrvCtrl->ulMemBase,pDrvCtrl->ulMemBase_dmaaddr);
pDrvCtrl->ulFreeSaRDs = pDrvCtrl->ulSaRDDescs;
pDrvCtrl->ulCurrSaRdReadPtr = 0;
pDrvCtrl->ulCurrSaRdWritePtr = 0;
pDrvCtrl->ulPkeBDMemBase = pDrvCtrl->ulMemBase + ulIPSecMemPoolSize + ulSaMemPoolSize;
pDrvCtrl->ulPkeBDMemBase_dmaaddr= pDrvCtrl->ulMemBase_dmaaddr+ ulIPSecMemPoolSize + ulSaMemPoolSize;
pDrvCtrl->ulFreePkeBDs = pDrvCtrl->ulPkeBDDescs;
pDrvCtrl->ulCurrPkeBdReadPtr = 0;
pDrvCtrl->ulCurrPkeBdWritePtr = 0;
pDrvCtrl->ulPkeRDMemBase = pDrvCtrl->ulPkeBDMemBase + pDrvCtrl->ulPkeBDDescs * (SSX31B_PKE_BD_LENGTH);
pDrvCtrl->ulPkeRDMemBase_dmaaddr= SSX31DRV_VIRT2DMA(pDrvCtrl->ulPkeRDMemBase, pDrvCtrl->ulMemBase,pDrvCtrl->ulMemBase_dmaaddr);
pDrvCtrl->ulFreePkeRDs = pDrvCtrl->ulPkeRDDescs;
pDrvCtrl->ulCurrPkeRdReadPtr = 0;
pDrvCtrl->ulCurrPkeRdWritePtr = 0;
for (i = 0; i < pDrvCtrl->ulIPSecBDDescs; i ++)
{
SSX31B_ICD* pICD;
SSX31B_IPSEC_BD* pCurBD = ((SSX31B_IPSEC_BD *)(pDrvCtrl->ulIPSecBDMemBase + i * SSX31B_IPSEC_BD_LENGTH));
pICD = &((SSX31B_ICD*)(pDrvCtrl->pstGather))[i * SSX31B_MAX_GATHER];
pICD->ulInputAttrib = 0;
pICD->ulInputLen = SSX31B_PE_HEADER_LEHGTN;
pICD->ulInputPtr = pDrvCtrl->ulCtrlWordMemBase_dmaaddr+ i * SSX31B_PE_HEADER_LEHGTN;
pCurBD->ulInputContext =SSX31DRV_VIRT2DMA(pICD, pDrvCtrl->pstGather,pDrvCtrl->pstGather_dmaaddr);
pCurBD->ulGatherEnable = 1;
}
return OK;
}
ULONG SSX31B_DMAInit(SSX31BDRV_CTRL* pDrvCtrl)
{
ULONG ulTmp;
/*DMA1 Sa*/
// PciWrite32(SSX31B_REG_BQBA1, virt_to_bus(pDrvCtrl->ulSaBDMemBase));
PciWrite32(SSX31B_REG_BQBA1, pDrvCtrl->ulSaBDMemBase_dmaaddr);
PciWrite32(SSX31B_REG_BQS1, pDrvCtrl->ulSaBDDescs - 1);
PciWrite32(SSX31B_REG_BQRP1, pDrvCtrl->ulCurrSaBdReadPtr);
PciWrite32(SSX31B_REG_BQWP1, pDrvCtrl->ulCurrSaBdWritePtr);
// PciWrite32(SSX31B_REG_RQBA1, virt_to_bus(pDrvCtrl->ulSaRDMemBase));
PciWrite32(SSX31B_REG_RQBA1, pDrvCtrl->ulSaRDMemBase_dmaaddr);
PciWrite32(SSX31B_REG_RQS1, pDrvCtrl->ulSaRDDescs - 1);
PciWrite32(SSX31B_REG_RQRP1, pDrvCtrl->ulCurrSaRdReadPtr );
PciWrite32(SSX31B_REG_RQWP1, pDrvCtrl->ulCurrSaRdWritePtr);
PciWrite32(SSX31B_REG_DMACTRL1, (DMA1_CTRL_CHANNEL_ENABLE | DMA1_CTRL_BURST_256 | DMA1_CTRL_DESC_BYTEORDER_SWAP));
// PciWrite32(SSX31B_REG_DMACTRL1, (DMA1_CTRL_CHANNEL_ENABLE | DMA1_CTRL_BURST_256));
ulTmp = SSX31B_BASIC_BD_LENGTH / sizeof(ULONG);
PciWrite32(SSX31B_REG_PDLR1, ulTmp);
PciWrite32(SSX31B_REG_BQTMOUT1, (DMA1_TIMEOUT_RD | DMA1_TIMEOUT_DMA1));
/*DMA2 Pke*/
// PciWrite32(SSX31B_REG_BQBA2, virt_to_bus(pDrvCtrl->ulPkeBDMemBase));
PciWrite32(SSX31B_REG_BQBA2, pDrvCtrl->ulPkeBDMemBase_dmaaddr);
PciWrite32(SSX31B_REG_BQS2, pDrvCtrl->ulPkeBDDescs - 1);
PciWrite32(SSX31B_REG_BQRP2, pDrvCtrl->ulCurrPkeBdReadPtr);
PciWrite32(SSX31B_REG_BQWP2, pDrvCtrl->ulCurrPkeBdWritePtr);
// PciWrite32(SSX31B_REG_RQBA2, virt_to_bus(pDrvCtrl->ulPkeRDMemBase));
PciWrite32(SSX31B_REG_RQBA2, pDrvCtrl->ulPkeRDMemBase_dmaaddr);
PciWrite32(SSX31B_REG_RQS2, pDrvCtrl->ulPkeRDDescs - 1);
PciWrite32(SSX31B_REG_RQRP2, pDrvCtrl->ulCurrPkeRdReadPtr );
PciWrite32(SSX31B_REG_RQWP2, pDrvCtrl->ulCurrPkeRdWritePtr);
PciWrite32(SSX31B_REG_DMACTRL2, (DMA2_CTRL_CHANNEL_ENABLE /* | DMA2_CTRL_BURST_256 */));
ulTmp = SSX31B_PKE_BD_LENGTH / sizeof(ULONG);
PciWrite32(SSX31B_REG_PDLR2, ulTmp);
PciWrite32(SSX31B_REG_BQTMOUT2, (DMA2_TIMEOUT_RD | DMA2_TIMEOUT_DMA2));
/*DMA3 IPSec*/
// PciWrite32(SSX31B_REG_BQBA3, virt_to_bus(pDrvCtrl->ulIPSecBDMemBase));
PciWrite32(SSX31B_REG_BQBA3, pDrvCtrl->ulIPSecBDMemBase_dmaaddr);
PciWrite32(SSX31B_REG_BQS3, pDrvCtrl->ulIPSecBDDescs - 1 );
PciWrite32(SSX31B_REG_BQRP3, pDrvCtrl->ulCurrIPSecBdReadPtr);
PciWrite32(SSX31B_REG_BQWP3, pDrvCtrl->ulCurrIPSecBdWritePtr);
// PciWrite32(SSX31B_REG_RQBA3, virt_to_bus(pDrvCtrl->ulIPSecRDMemBase));
PciWrite32(SSX31B_REG_RQBA3, pDrvCtrl->ulIPSecRDMemBase_dmaaddr);
PciWrite32(SSX31B_REG_RQS3, pDrvCtrl->ulIPSecRDDescs - 1);
PciWrite32(SSX31B_REG_RQRP3, pDrvCtrl->ulCurrIPSecRdReadPtr);
PciWrite32(SSX31B_REG_RQWP3, pDrvCtrl->ulCurrIPSecRdWritePtr);
PciWrite32(SSX31B_REG_DMACTRL3, DMA3_CTRL_CHANNEL_ENABLE);
ulTmp = SSX31B_IPSEC_BD_LENGTH / sizeof(ULONG);
PciWrite32(SSX31B_REG_PDLR3, ulTmp);
PciWrite32(SSX31B_REG_BQTMOUT3, (DMA3_TIMEOUT_RD | DMA3_TIMEOUT_DMA3));
return OK;
}
ULONG SSX31B_ISRInit(SSX31BDRV_CTRL* pDrvCtrl)
{
/* PciWrite32(SSX31B_REG_INT_MASK, INT_STAT_DMA3_PACK_DONE); */
return OK;
}
ULONG SSX31B_DeviceInit(SSX31BDRV_CTRL* pDrvCtrl)
{
SSX31B_PCInit(pDrvCtrl);
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