?? frequency.map.rpt
字號:
; 2:1 ; 15 bits ; 15 LEs ; 15 LEs ; 0 LEs ; No ; |Frequency|lpm_divide:inst6|sign_div_unsign:divider|alt_u_div:divider|StageOut[17][4]~643 ;
; 2:1 ; 15 bits ; 15 LEs ; 15 LEs ; 0 LEs ; No ; |Frequency|lpm_divide:inst6|sign_div_unsign:divider|alt_u_div:divider|StageOut[18][14]~668 ;
; 2:1 ; 15 bits ; 15 LEs ; 15 LEs ; 0 LEs ; No ; |Frequency|lpm_divide:inst6|sign_div_unsign:divider|alt_u_div:divider|StageOut[19][2]~671 ;
; 2:1 ; 15 bits ; 15 LEs ; 15 LEs ; 0 LEs ; No ; |Frequency|lpm_divide:inst6|sign_div_unsign:divider|alt_u_div:divider|StageOut[20][14]~698 ;
; 2:1 ; 15 bits ; 15 LEs ; 15 LEs ; 0 LEs ; No ; |Frequency|lpm_divide:inst6|sign_div_unsign:divider|alt_u_div:divider|StageOut[21][14]~713 ;
; 2:1 ; 15 bits ; 15 LEs ; 15 LEs ; 0 LEs ; No ; |Frequency|lpm_divide:inst6|sign_div_unsign:divider|alt_u_div:divider|StageOut[22][15]~729 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 678 ;
; Number of synthesis-generated cells ; 829 ;
; Number of WYSIWYG LUTs ; 678 ;
; Number of synthesis-generated LUTs ; 741 ;
; Number of WYSIWYG registers ; 8 ;
; Number of synthesis-generated registers ; 120 ;
; Number of cells with combinational logic only ; 1379 ;
; Number of cells with registers only ; 88 ;
; Number of cells with combinational logic and registers ; 40 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 128 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 40 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 32 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------+
; Hierarchy ;
+-----------+
Frequency
|-- INTIGRATOR_FE:inst
|-- lpm_counter:CYCLE_rtl_0
|-- cntr_ia7:auto_generated
|-- lpm_divide:inst1
|-- sign_div_unsign:divider
|-- lpm_add_sub:adder
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- alt_u_div:divider
|-- lpm_add_sub:$00003
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00005
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00007
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00009
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00011
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00013
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00015
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00017
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00019
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00021
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00023
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00025
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:$00027
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
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