;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  $Workfile:   LH7A400_evb_get_dipsw.s  $
;  $Revision:   1.0  $
;  $Author:   WellsK  $
;  $Date:   Sep 23 2002 13:52:04  $
; 
;  Project: 
; 
;  Description:
; 
;  Revision History:
;  $Log:   //smaicnt2/pvcs/VM/CDROM/archives/KEV7A400/Software/Startup_lite/LH7A400_evb_get_dipsw.s-arc  $
; 
;    Rev 1.0   Sep 23 2002 13:52:04   WellsK
; Initial revision.
; 
;    Rev 1.0   Sep 14 2002 11:38:08   WellsK
; Initial revision.
; 
;    Rev 1.0   Jun 13 2002 14:40:22   BarnettH
; Initial revision.
;  
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  
;   Copyright (c) 2002 Sharp Microelectronics of the Americas
; 
;   All rights reserved
; 
;   SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
;   OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
;   AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
;   SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
; 
;   SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
;   FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
;   SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT.  USE OF THIS SOURCE
;   FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
; 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; word LH7A400_evb_get_dipsw (word mode)
;
; Purpose:
;   To return the current value of DIP Switch S1 HW on the
;   LH7A400 EVB CPU Board or Display Board.
;
; Processing:
;   Compare argument mode (r0)
;   Initialize SMC BCR for CPLD
;   if (mode == CPU_DIP_SWITCH)
;      Get current CPU DIP switch value into r0
;      Store CPU DIP switch value
;   else (mode != CPU_DIP_SWITCH)
;      Get current DISP DIP switch value into r0
;      Store DISP DIP switch value
;      return r0
;
;   Uses r0, r1, cpsr registers
;   Destroys contents of r0, r1 registers
;   May change cpsr status bits
;
; Parameters:
;   Parameter mode: r0 == 0, get CPU DIP Switch setting
;   Parameter mode: r0 != 0, get DISP DIP Switch setting
;
; Outputs: None.
;
; Returns:  DIP Switch S1 current state for selected board
;   in r0.  (<bit> == 0, switch OFF; <bit> == 1, switch ON)
;
; C Prototype:
;   UNS_32 LH7A400_evb_get_dipsw (UNS_32 mode)
;
; Notes: 
;    (1) Callable from C or assembly.
;    (2) Does not use the stack; may be called with no stack
;        initialized.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    AREA    UTILS_ASM, CODE, ALIGN=2

    INCLUDE LH7A400_evb.i

    EXPORT  LH7A400_evb_get_dipsw

LH7A400_evb_get_dipsw    ROUT
    ; ? CPU
    CMP     r0, #0 
    ; Ensure SMC_BCR2 (CPLD) is initialized
    LDR     r0, =SMC_REG_BASE
    LDR     r1, =SMC_BCR2_INIT
    STR     r1, [r0,#SMC_BCR2_OFFSET]
    ; Get CPU DIP Switch S1 state.
    LDR     r1, =CPLD_REG_BASE
    LDREQH    r0, [r1,#CPLD_CPUDIPSW_OFFSET]
    LDRNEH    r0, [r1,#CPLD_DISPDIPSW_OFFSET]
    AND     r0, r0, #0xFF   ; Only bits 7-0 valid
    ; Store current DIP SW1 HW setting 
    LDREQ     r1, =CPU_DIPSW_STORE_ADDR
    LDRNE     r1, =DISP_DIPSW_STORE_ADDR
    STR     r0, [r1]
    ; Return DIP SW1 value
    MOV     pc, r14

    END