?? control.vhd
字號(hào):
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"4119000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"33333333333332CCCF3333333CCCCCCCCCCAAED8D0A3D03D78FD7DD34088F3CF",
INITP_01 => X"CFFF3B82A8838E0E228FAA8F80A3EA8F02E28E2DCB72DCB72D2CB33333333333",
INITP_02 => X"00000000000000000000000000000000000000000000000C834ACB0B0DBF3333",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"C000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DIB => "0000000000000000",
DIPB => "00",
ENB => '1',
WEB => '0',
SSRB => '0',
CLKB => clk,
ADDRB => address,
DOB => instruction(15 downto 0),
DOPB => instruction(17 downto 16),
DIA => jdata,
DIPA => jparity,
ENA => sel1,
WEA => '1',
SSRA => '0',
CLKA => update,
ADDRA=> jaddr,
DOA => doa(7 downto 0),
DOPA => dopa);
--buffer signal used as a clock
upload_clock: BUFG
port map( I => drck1,
O => drck1_buf);
-- Assign the reset to be active whenever the uploading subsystem is active
proc_reset <= sel1;
srlC1: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tdi,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(10),
Q15 => jaddr(8));
flop1: FD
port map ( D => jaddr(10),
Q => jaddr(9),
C => drck1_buf);
srlC2: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jaddr(8),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(7),
Q15 => tap5);
flop2: FD
port map ( D => jaddr(7),
Q => jaddr(6),
C => drck1_buf);
srlC3: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tap5,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(5),
Q15 => jaddr(3));
flop3: FD
port map ( D => jaddr(5),
Q => jaddr(4),
C => drck1_buf);
srlC4: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jaddr(3),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(2),
Q15 => tap11);
flop4: FD
port map ( D => jaddr(2),
Q => jaddr(1),
C => drck1_buf);
srlC5: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tap11,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(0),
Q15 => jdata(7));
flop5: FD
port map ( D => jaddr(0),
Q => jparity(0),
C => drck1_buf);
srlC6: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jdata(7),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jdata(6),
Q15 => tap17);
flop6: FD
port map ( D => jdata(6),
Q => jdata(5),
C => drck1_buf);
srlC7: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tap17,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jdata(4),
Q15 => jdata(2));
flop7: FD
port map ( D => jdata(4),
Q => jdata(3),
C => drck1_buf);
srlC8: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jdata(2),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jdata(1),
Q15 => tdo1);
flop8: FD
port map ( D => jdata(1),
Q => jdata(0),
C => drck1_buf);
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE control.vhd
--
------------------------------------------------------------------------------------
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