#-- Synplicity, Inc.
#-- Version Synplify Pro 8.8
#-- Project file R:\training\desperf\labs\synthesis\synplify\vhdl\run_options.txt
#-- Written on Fri Mar 16 10:29:31 2007


#add_file options
add_file -vhdl -lib work "correlate_and_accumulate_pack.vhd"
add_file -vhdl -lib work "mac_ch.vhd"
add_file -vhdl -lib work "read_ch_arbiter.vhd"
add_file -vhdl -lib work "mac.vhd"
add_file -vhdl -lib work "data_output_mux.vhd"
add_file -vhdl -lib work "data_control_fsm.vhd"
add_file -vhdl -lib work "data_control.vhd"
add_file -constraint "R:/training/desperf/labs/synthesis/synplify/vhdl/data_control.sdc"


#implementation: "vhdl"
impl -add vhdl -type fpga

#device options
set_option -technology VIRTEX4
set_option -part xc4vlx15
set_option -package sf363
set_option -speed_grade -12
set_option -part_companion ""

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -use_fsm_explorer 1
set_option -top_module "data_control"

#map options
set_option -frequency 400.000
set_option -run_prop_extract 1
set_option -fanout_limit 200
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 0

#set result format/file last
project -result_file "./data_control.edn"

#
#implementation attributes

set_option -vlog_std v2001
set_option -num_critical_paths 0
set_option -num_startend_points 0
impl -active "vhdl"