?? 復件 (2) main.c
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}
//判斷定時器
void hspdtc0()
{
//AIC_IDCR |= set_12; //AIC中斷禁用命令寄存器
if(uz_zd1msyd != 0)
{
uz_zd1msyd = 0;
uz_1msyd = 1;
}
//AIC_IECR |= set_12; //AIC中斷使能命令寄存器
}
//清定時器
void hsqdsq()
{
uz_1msyd = 0;
uz_10msyd = 0;
uz_100msyd = 0;
uz_1syd = 0;
}
//輸入處理
unsigned char a0;
unsigned char a1;
unsigned char a2;
unsigned char a3;
void ws_hssrcl(unsigned long *ul_ccs,unsigned long *ul_srycz)
{
}
//輸出
void ws_hssc(void)
{
// PIO_ODSR = ul_sc;
}
#define set_s PIO_SODR = set_8
#define clr_s PIO_CODR = set_8
#define set_cp1 PIO_SODR = set_9
#define clr_cp1 PIO_CODR = set_9
#define set_cp2 PIO_SODR = set_10
#define clr_cp2 PIO_CODR = set_10
#define set_disp PIO_SODR = set_24
#define clr_disp PIO_CODR = set_24
//液晶驅動
void hsyjcl(void)
{
unsigned char y;
PIO_ODSR &= 0xfffffff0;
clr_disp;
{
y = 239;
set_disp;
set_disp;
clr_s;
clr_s;
set_cp1;
set_cp1;
set_s;
set_s;
clr_cp1;
clr_cp1;
clr_cp2;
clr_cp2;
clr_s;
clr_s;
set_disp;
set_disp;
while (y!=0)
{
hsqkmg(); //清看門狗
{
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //0
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //1
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //2
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //3
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //4
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //5
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2;//6
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //7
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //8
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //9
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //10
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //11
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //12
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //13
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2;//14
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //15
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //16
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //17
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //18
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //19
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //20
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //21
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //22
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //23
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //24
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //25
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2;//26
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //27
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //28
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //29
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //30
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //31
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //32
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //33
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //34
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //35
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2;//36
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //37
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //38
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //39
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //40
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //41
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //42
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //43
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //44
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //45
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2;//46
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //47
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //48
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //49
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //50
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //51
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //52
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //53
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //54
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //55
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2;//56
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //57
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //58
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //59
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //60
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //61
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //62
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //63
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //64
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //65
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2;//66
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //67
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //68
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //69
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //70
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //71
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //72
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //73
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //74
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //75
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2;//76
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //77
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //78
PIO_ODSR |= 0xa;
set_cp2;
clr_cp2; //79
}
set_cp1;
set_cp1;
--y;
clr_cp1;
clr_cp1;
}
clr_disp;
}
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