Release 10.1.02 par K.37 (nt)Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.PHILIP::  Sun Aug 24 13:07:29 2008par -w -intstyle ise -ol std -t 1 DDR_6TO1_16CHAN_RT_RX_map.ncd
DDR_6TO1_16CHAN_RT_RX.ncd DDR_6TO1_16CHAN_RT_RX.pcf Constraints file: DDR_6TO1_16CHAN_RT_RX.pcf.Loading device for application Rf_Device from file '5vsx50t.nph' in environment K:\Xilinx\10.1\ISE.   "DDR_6TO1_16CHAN_RT_RX" is an NCD, version 3.2, device xc5vsx50t, package ff1136, speed -1Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".Device speed data version:  "PRODUCTION 1.61 2008-05-28".Device Utilization Summary:   Number of BUFGs                           2 out of 32      6%   Number of BUFIOs                          1 out of 56      1%   Number of BUFRs                           1 out of 24      4%   Number of IDELAYCTRLs                     1 out of 16      6%   Number of External IOBs                 215 out of 480    44%      Number of LOCed IOBs                   0 out of 215     0%   Number of IODELAYs                       35 out of 560     6%   Number of ISERDESs                       34 out of 560     6%   Number of RAMB36SDP_EXPs                  1 out of 132     1%   Number of Slice Registers               502 out of 32640   1%      Number used as Flip Flops            502      Number used as Latches                 0      Number used as LatchThrus              0   Number of Slice LUTS                    718 out of 32640   2%   Number of Slice LUT-Flip Flop pairs     865 out of 32640   2%Overall effort level (-ol):   Standard Router effort level (-rl):    Standard Starting RouterPhase 1: 4874 unrouted;       REAL time: 16 secs Phase 2: 4418 unrouted;       REAL time: 16 secs Phase 3: 1983 unrouted;       REAL time: 19 secs Phase 4: 1983 unrouted; (0)      REAL time: 25 secs Phase 5: 2009 unrouted; (0)      REAL time: 26 secs Phase 6: 0 unrouted; (0)      REAL time: 29 secs Updating file: DDR_6TO1_16CHAN_RT_RX.ncd with current fully routed design.Phase 7: 0 unrouted; (0)      REAL time: 29 secs Phase 8: 0 unrouted; (0)      REAL time: 29 secs Phase 9: 0 unrouted; (0)      REAL time: 30 secs Phase 10: 0 unrouted; (0)      REAL time: 31 secs Total REAL time to Router completion: 31 secs Total CPU time to Router completion: 29 secs Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|       RXCLKDIV_OBUF |  Regional Clk| No   |  239 |  0.928     |  1.894      |+---------------------+--------------+------+------+------------+-------------+|     RXCLK_USR_BUFGP |BUFGCTRL_X0Y24| No   |   25 |  0.408     |  1.915      |+---------------------+--------------+------+------+------------+-------------+|          RXCLK_TEMP |        IO Clk| No   |   68 |  0.128     |  0.425      |+---------------------+--------------+------+------+------------+-------------+|        CLK200_BUFGP |BUFGCTRL_X0Y26| No   |    1 |  0.000     |  1.825      |+---------------------+--------------+------+------+------------+-------------+* Net Skew is the difference between the minimum and maximum routingonly delays for the net. Note this is different from Clock Skew whichis reported in TRCE timing report. Clock Skew is the difference betweenthe minimum and maximum path delays which includes logic delays.Timing Score: 0INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
   requested value.Asterisk (*) preceding a constraint indicates it was not met.   This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing                                               |         |    Slack   | Achievable | Errors |    Score   ------------------------------------------------------------------------------------------------------  Autotimespec constraint for clock net RXC | SETUP   |         N/A|     4.670ns|     N/A|           0  LKDIV_OBUF                                | HOLD    |     0.277ns|            |       0|           0------------------------------------------------------------------------------------------------------  Autotimespec constraint for clock net RXC | SETUP   |         N/A|     3.323ns|     N/A|           0  LK_USR_BUFGP                              | HOLD    |     0.486ns|            |       0|           0------------------------------------------------------------------------------------------------------All constraints were met.INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the    constraint does not cover any paths or that it has no requested value.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 45 secs Total CPU time to PAR completion: 41 secs Peak Memory Usage:  302 MBPlacer: Placement generated during map.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 2Writing design to file DDR_6TO1_16CHAN_RT_RX.ncdPAR done!