Release 10.1.02 par K.37 (nt)Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.PHILIP::  Mon Aug 25 17:18:25 2008par -w -intstyle ise -ol std -t 1 lvds_tx_rx_merge_map.ncd lvds_tx_rx_merge.ncd
lvds_tx_rx_merge.pcf Constraints file: lvds_tx_rx_merge.pcf.Loading device for application Rf_Device from file '5vsx50t.nph' in environment K:\Xilinx\10.1\ISE.   "lvds_tx_rx_merge" is an NCD, version 3.2, device xc5vsx50t, package ff1136, speed -1Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)Device speed data version:  "PRODUCTION 1.61 2008-05-28".Device Utilization Summary:   Number of BUFGs                           4 out of 32     12%   Number of BUFIOs                          1 out of 56      1%   Number of BUFRs                           1 out of 24      4%   Number of IDELAYCTRLs                     1 out of 16      6%   Number of External IOBs                 291 out of 480    60%      Number of LOCed IOBs                   0 out of 291     0%   Number of External IOBMs                 18 out of 240     7%      Number of LOCed IOBMs                  0 out of 18      0%   Number of External IOBSs                 18 out of 240     7%      Number of LOCed IOBSs                  0 out of 18      0%   Number of IODELAYs                       35 out of 560     6%   Number of ISERDESs                       34 out of 560     6%   Number of OLOGICs                        67 out of 560    11%   Number of OSERDESs                       17 out of 560     3%   Number of RAMB36SDP_EXPs                  2 out of 132     1%   Number of Slice Registers               675 out of 32640   2%      Number used as Flip Flops            675      Number used as Latches                 0      Number used as LatchThrus              0   Number of Slice LUTS                    811 out of 32640   2%   Number of Slice LUT-Flip Flop pairs    1048 out of 32640   3%Overall effort level (-ol):   Standard Router effort level (-rl):    Standard Starting initial Timing Analysis.  REAL time: 16 secs Finished initial Timing Analysis.  REAL time: 16 secs Starting RouterPhase 1: 6012 unrouted;       REAL time: 18 secs Phase 2: 5149 unrouted;       REAL time: 18 secs Phase 3: 1995 unrouted;       REAL time: 21 secs Phase 4: 1995 unrouted; (6539)      REAL time: 28 secs Phase 5: 2004 unrouted; (0)      REAL time: 29 secs Phase 6: 2004 unrouted; (0)      REAL time: 29 secs Phase 7: 0 unrouted; (0)      REAL time: 31 secs Updating file: lvds_tx_rx_merge.ncd with current fully routed design.Phase 8: 0 unrouted; (0)      REAL time: 32 secs Phase 9: 0 unrouted; (0)      REAL time: 32 secs Phase 10: 0 unrouted; (0)      REAL time: 33 secs Total REAL time to Router completion: 33 secs Total CPU time to Router completion: 30 secs Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|       RXCLKDIV_OBUF |  Regional Clk| No   |  240 |  0.908     |  1.874      |+---------------------+--------------+------+------+------------+-------------+|         TXCLK_BUFGP |BUFGCTRL_X0Y12| No   |   18 |  0.117     |  1.786      |+---------------------+--------------+------+------+------------+-------------+|       CLK_USR_BUFGP | BUFGCTRL_X0Y3| No   |  114 |  0.529     |  2.054      |+---------------------+--------------+------+------+------------+-------------+|      TXCLKDIV_BUFGP |BUFGCTRL_X0Y29| No   |   92 |  0.241     |  1.786      |+---------------------+--------------+------+------+------------+-------------+|        CLK200_BUFGP | BUFGCTRL_X0Y2| No   |    1 |  0.000     |  1.825      |+---------------------+--------------+------+------+------------+-------------+|   uut_rx/RXCLK_TEMP |        IO Clk| No   |   68 |  0.128     |  0.425      |+---------------------+--------------+------+------+------------+-------------+* Net Skew is the difference between the minimum and maximum routingonly delays for the net. Note this is different from Clock Skew whichis reported in TRCE timing report. Clock Skew is the difference betweenthe minimum and maximum path delays which includes logic delays.Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.   This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing                                               |         |    Slack   | Achievable | Errors |    Score   ------------------------------------------------------------------------------------------------------  TS_CLK_USR = PERIOD TIMEGRP "CLK_USR" 6 n | SETUP   |     0.273ns|     5.727ns|       0|           0  s HIGH 50%                                | HOLD    |     0.369ns|            |       0|           0------------------------------------------------------------------------------------------------------  TS_TXCLKDIV = PERIOD TIMEGRP "TXCLKDIV" 6 | SETUP   |     0.716ns|     5.284ns|       0|           0   ns HIGH 50%                              | HOLD    |     0.400ns|            |       0|           0------------------------------------------------------------------------------------------------------All constraints were met.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 46 secs Total CPU time to PAR completion: 42 secs Peak Memory Usage:  305 MBPlacer: Placement generated during map.Routing: Completed - No errors found.Timing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 0Writing design to file lvds_tx_rx_merge.ncdPAR done!