Release 10.1.02 Map K.37 (nt)Xilinx Map Application Log File for Design 'DDR_6TO1_16CHAN_RT_TX'Design Information------------------Command Line   : map -ise E:/ISEworks/LVDS/xapp860/xapp860.ise -intstyle ise -p
xc5vsx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -cm area -pr off -k 6 -lc off
-power off -o DDR_6TO1_16CHAN_RT_TX_map.ncd DDR_6TO1_16CHAN_RT_TX.ngd
DDR_6TO1_16CHAN_RT_TX.pcf Target Device  : xc5vsx50tTarget Package : ff1136Target Speed   : -1Mapper Version : virtex5 -- $Revision: 1.46.12.2 $Mapped Date    : Wed Aug 20 08:57:47 2008Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).Running timing-driven packing...Phase 1.1Phase 1.1 (Checksum:e7d1) REAL time: 7 secs Phase 2.7Phase 2.7 (Checksum:e7d1) REAL time: 8 secs Phase 3.31Phase 3.31 (Checksum:e7d1) REAL time: 8 secs Phase 4.33Phase 4.33 (Checksum:e7d1) REAL time: 8 secs Phase 5.32Phase 5.32 (Checksum:e7d1) REAL time: 8 secs Phase 6.2....Phase 6.2 (Checksum:460ac) REAL time: 9 secs Phase 7.30Phase 7.30 (Checksum:460ac) REAL time: 9 secs Phase 8.3...Phase 8.3 (Checksum:4cfad) REAL time: 10 secs Phase 9.5Phase 9.5 (Checksum:4cfad) REAL time: 10 secs Phase 10.8.Phase 10.8 (Checksum:c50ac) REAL time: 10 secs Phase 11.29Phase 11.29 (Checksum:c50ac) REAL time: 10 secs Phase 12.5Phase 12.5 (Checksum:c50ac) REAL time: 10 secs Phase 13.18Phase 13.18 (Checksum:c42d7) REAL time: 13 secs Phase 14.5Phase 14.5 (Checksum:c42d7) REAL time: 13 secs Phase 15.34Phase 15.34 (Checksum:c42d7) REAL time: 13 secs REAL time consumed by placer: 13 secs CPU  time consumed by placer: 12 secs Design Summary--------------Design Summary:Number of errors:      0Number of warnings:   17Slice Logic Utilization:  Number of Slice Registers:                    96 out of  32,640    1%    Number used as Flip Flops:                  96  Number of Slice LUTs:                         48 out of  32,640    1%    Number used as logic:                       48 out of  32,640    1%      Number using O6 output only:              48Slice Logic Distribution:  Number of occupied Slices:                    70 out of   8,160    1%  Number of LUT Flip Flop pairs used:           96    Number with an unused Flip Flop:             0 out of      96    0%    Number with an unused LUT:                  48 out of      96   50%    Number of fully used LUT-FF pairs:          48 out of      96   50%    Number of unique control sets:              49    Number of slice register sites lost      to control set restrictions:             144 out of  32,640    1%  A LUT Flip Flop pair for this architecture represents one LUT paired with  one Flip Flop within a slice.  A control set is a unique combination of  clock, reset, set, and enable signals for a registered element.  The Slice Logic Distribution report is not meaningful if the design is  over-mapped for a non-slice resource or if Placement fails.IO Utilization:  Number of bonded IOBs:                       134 out of     480   27%    IOB Flip Flops:                              1    IOB Master Pads:                            17    IOB Slave Pads:                             17Specific Feature Utilization:  Number of BUFG/BUFGCTRLs:                      2 out of      32    6%    Number used as BUFGs:                        2  Number of OSERDESs:                           16Peak Memory Usage:  355 MBTotal REAL time to MAP completion:  25 secs Total CPU time to MAP completion:   24 secs Mapping completed.See MAP report file "DDR_6TO1_16CHAN_RT_TX_map.mrp" for details.