Release 10.1.02 par K.37 (nt)Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.PHILIP::  Tue Aug 19 20:16:16 2008par -w -intstyle ise -ol std -t 1 BIT_ALIGN_MACHINE_map.ncd
BIT_ALIGN_MACHINE.ncd BIT_ALIGN_MACHINE.pcf Constraints file: BIT_ALIGN_MACHINE.pcf.Loading device for application Rf_Device from file '5vsx50t.nph' in environment K:\Xilinx\10.1\ISE.   "BIT_ALIGN_MACHINE" is an NCD, version 3.2, device xc5vsx50t, package ff1136, speed -1Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".Device speed data version:  "PRODUCTION 1.61 2008-05-28".Device Utilization Summary:   Number of BUFGs                           1 out of 32      3%   Number of External IOBs                  14 out of 480     2%      Number of LOCed IOBs                   0 out of 14      0%   Number of Slice Registers                33 out of 32640   1%      Number used as Flip Flops             33      Number used as Latches                 0      Number used as LatchThrus              0   Number of Slice LUTS                     76 out of 32640   1%   Number of Slice LUT-Flip Flop pairs      76 out of 32640   1%Overall effort level (-ol):   Standard Router effort level (-rl):    Standard Starting RouterPhase 1: 428 unrouted;       REAL time: 18 secs Phase 2: 413 unrouted;       REAL time: 18 secs Phase 3: 211 unrouted;       REAL time: 19 secs Phase 4: 211 unrouted; (0)      REAL time: 27 secs Phase 5: 215 unrouted; (0)      REAL time: 27 secs Phase 6: 0 unrouted; (0)      REAL time: 27 secs Updating file: BIT_ALIGN_MACHINE.ncd with current fully routed design.Phase 7: 0 unrouted; (0)      REAL time: 27 secs Phase 8: 0 unrouted; (0)      REAL time: 27 secs Phase 9: 0 unrouted; (0)      REAL time: 27 secs Phase 10: 0 unrouted; (0)      REAL time: 28 secs Total REAL time to Router completion: 28 secs Total CPU time to Router completion: 26 secs Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|      RXCLKDIV_BUFGP | BUFGCTRL_X0Y0| No   |   14 |  0.044     |  1.641      |+---------------------+--------------+------+------+------------+-------------+* Net Skew is the difference between the minimum and maximum routingonly delays for the net. Note this is different from Clock Skew whichis reported in TRCE timing report. Clock Skew is the difference betweenthe minimum and maximum path delays which includes logic delays.Timing Score: 0INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
   requested value.Asterisk (*) preceding a constraint indicates it was not met.   This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing                                               |         |    Slack   | Achievable | Errors |    Score   ------------------------------------------------------------------------------------------------------  Autotimespec constraint for clock net RXC | SETUP   |         N/A|     3.886ns|     N/A|           0  LKDIV_BUFGP                               | HOLD    |     0.495ns|            |       0|           0------------------------------------------------------------------------------------------------------All constraints were met.INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the    constraint does not cover any paths or that it has no requested value.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 42 secs Total CPU time to PAR completion: 38 secs Peak Memory Usage:  284 MBPlacer: Placement generated during map.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 2Writing design to file BIT_ALIGN_MACHINE.ncdPAR done!