---------------------------------------------------------------------------------- Company: -- Engineer:---- Create Date:   10:49:54 08/20/2008-- Design Name:   -- Module Name:   E:/ISEworks/LVDS/xapp860/lvds_vhd_tb.vhd-- Project Name:  xapp860-- Target Device:  -- Tool versions:  -- Description:   -- -- VHDL Test Bench Created by ISE for module: DDR_6TO1_16CHAN_RT_RX-- -- Dependencies:-- -- Revision:-- Revision 0.01 - File Created-- Additional Comments:---- Notes: -- This testbench has been automatically generated using types std_logic and-- std_logic_vector for the ports of the unit under test.  Xilinx recommends-- that these types always be used for the top-level I/O of a design in order-- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model.--------------------------------------------------------------------------------LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL; ENTITY lvds_vhd_tb ISEND lvds_vhd_tb; ARCHITECTURE behavior OF lvds_vhd_tb IS      -- Component Declaration for the Unit Under Test (UUT)     COMPONENT DDR_6TO1_16CHAN_RT_RX    PORT(         DATA_RX_P : IN  std_logic_vector(15 downto 0);         DATA_RX_N : IN  std_logic_vector(15 downto 0);         CLOCK_RX_P : IN  std_logic;         CLOCK_RX_N : IN  std_logic;         INC_PAD : IN  std_logic;         DEC_PAD : IN  std_logic;         DATA_FROM_ISERDES : OUT  std_logic_vector(95 downto 0);         RESET : IN  std_logic;         IDLY_RESET : IN  std_logic;         IDELAYCTRL_RESET : IN  std_logic;         BITSLIP_PAD : IN  std_logic;         CLK200 : IN  std_logic;         TAP_00 : OUT  std_logic_vector(5 downto 0);         TAP_01 : OUT  std_logic_vector(5 downto 0);         TAP_02 : OUT  std_logic_vector(5 downto 0);         TAP_03 : OUT  std_logic_vector(5 downto 0);         TAP_04 : OUT  std_logic_vector(5 downto 0);         TAP_05 : OUT  std_logic_vector(5 downto 0);         TAP_06 : OUT  std_logic_vector(5 downto 0);         TAP_07 : OUT  std_logic_vector(5 downto 0);         TAP_08 : OUT  std_logic_vector(5 downto 0);         TAP_09 : OUT  std_logic_vector(5 downto 0);         TAP_10 : OUT  std_logic_vector(5 downto 0);         TAP_11 : OUT  std_logic_vector(5 downto 0);         TAP_12 : OUT  std_logic_vector(5 downto 0);         TAP_13 : OUT  std_logic_vector(5 downto 0);         TAP_14 : OUT  std_logic_vector(5 downto 0);         TAP_15 : OUT  std_logic_vector(5 downto 0);         TAP_CLK : OUT  std_logic_vector(5 downto 0);         TRAINING_DONE : OUT  std_logic;         RXCLK : OUT  std_logic;         RXCLKDIV : OUT  std_logic;         IDELAY_READY : OUT  std_logic;         RT_MANUAL_DISABLE : IN  std_logic        );    END COMPONENT;    	 COMPONENT DDR_6TO1_16CHAN_RT_TX    PORT(         DATA_TX_P : OUT  std_logic_vector(15 downto 0);         DATA_TX_N : OUT  std_logic_vector(15 downto 0);         CLOCK_TX_P : OUT  std_logic;         CLOCK_TX_N : OUT  std_logic;         TXCLK : IN  std_logic;         TXCLKDIV : IN  std_logic;         DATA_TO_OSERDES : IN  std_logic_vector(95 downto 0);         RESET : IN  std_logic;         TRAINING_DONE : IN  std_logic        );    END COMPONENT;   --Inputs   signal DATA_RX_P : std_logic_vector(15 downto 0);-- := (others => '0');   signal DATA_RX_N : std_logic_vector(15 downto 0);-- := (others => '0');   signal CLOCK_RX_P : std_logic;-- := '0';--   signal CLOCK_RX_N : std_logic;-- := '0';--   signal INC_PAD : std_logic := '0';   signal DEC_PAD : std_logic := '0';   signal RESET : std_logic := '1';   signal IDLY_RESET : std_logic := '1';   signal IDELAYCTRL_RESET : std_logic := '1';   signal BITSLIP_PAD : std_logic := '0';   signal CLK200 : std_logic := '0';   signal RT_MANUAL_DISABLE : std_logic := '0';		--Inputs   signal TXCLK : std_logic := '0';   signal TXCLKDIV : std_logic := '0';   signal DATA_TO_OSERDES : std_logic_vector(95 downto 0) := "101110101000101100101010101100101000100100101100101101001100101100101000101100100100101010101100";   --signal RESET : std_logic := '0';   signal TRAINING_DONE : std_logic := '0'; 	--Outputs   signal DATA_TX_P : std_logic_vector(15 downto 0);   signal DATA_TX_N : std_logic_vector(15 downto 0);   signal CLOCK_TX_P : std_logic;   signal CLOCK_TX_N : std_logic; 	--Outputs   signal DATA_FROM_ISERDES : std_logic_vector(95 downto 0);   signal TAP_00 : std_logic_vector(5 downto 0);   signal TAP_01 : std_logic_vector(5 downto 0);   signal TAP_02 : std_logic_vector(5 downto 0);   signal TAP_03 : std_logic_vector(5 downto 0);   signal TAP_04 : std_logic_vector(5 downto 0);   signal TAP_05 : std_logic_vector(5 downto 0);   signal TAP_06 : std_logic_vector(5 downto 0);   signal TAP_07 : std_logic_vector(5 downto 0);   signal TAP_08 : std_logic_vector(5 downto 0);   signal TAP_09 : std_logic_vector(5 downto 0);   signal TAP_10 : std_logic_vector(5 downto 0);   signal TAP_11 : std_logic_vector(5 downto 0);   signal TAP_12 : std_logic_vector(5 downto 0);   signal TAP_13 : std_logic_vector(5 downto 0);   signal TAP_14 : std_logic_vector(5 downto 0);   signal TAP_15 : std_logic_vector(5 downto 0);   signal TAP_CLK : std_logic_vector(5 downto 0);   --signal TRAINING_DONE : std_logic;   signal RXCLK : std_logic;   signal RXCLKDIV : std_logic;   signal IDELAY_READY : std_logic;   constant CLK200_period:time := 5 ns;	constant TXCLK_period:time := 3 ns;	constant TXCLKDIV_period:time := 9 ns;		constant delay1:time := 10 ns;	constant delay2:time := 20 ns;	constant delay3:time := 30 ns;	constant delay4:time := 40 ns;	constant delay5:time := 50 ns;	constant delay6:time := 60 ns;	constant delay7:time := 70 ns;	constant delay8:time := 80 ns;	constant delay9:time := 120 ns;	constant delay10:time := 200 ns;	constant delay11:time := 300 ns;	constant delay12:time := 400 ns;	constant delay13:time := 500 ns;	constant delay14:time := 600 ns;	constant delay15:time := 700 ns;	constant delay16:time := 800 ns;	BEGIN 	-- Instantiate the Unit Under Test (UUT)   uut_rx: DDR_6TO1_16CHAN_RT_RX PORT MAP (          DATA_RX_P => DATA_RX_P,          DATA_RX_N => DATA_RX_N,          CLOCK_RX_P => CLOCK_RX_P,          CLOCK_RX_N => CLOCK_RX_N,          INC_PAD => INC_PAD,          DEC_PAD => DEC_PAD,          DATA_FROM_ISERDES => DATA_FROM_ISERDES,          RESET => RESET,          IDLY_RESET => IDLY_RESET,          IDELAYCTRL_RESET => IDELAYCTRL_RESET,          BITSLIP_PAD => BITSLIP_PAD,          CLK200 => CLK200,          TAP_00 => TAP_00,          TAP_01 => TAP_01,          TAP_02 => TAP_02,          TAP_03 => TAP_03,          TAP_04 => TAP_04,          TAP_05 => TAP_05,          TAP_06 => TAP_06,          TAP_07 => TAP_07,          TAP_08 => TAP_08,          TAP_09 => TAP_09,          TAP_10 => TAP_10,          TAP_11 => TAP_11,          TAP_12 => TAP_12,          TAP_13 => TAP_13,          TAP_14 => TAP_14,          TAP_15 => TAP_15,          TAP_CLK => TAP_CLK,          TRAINING_DONE => TRAINING_DONE,          RXCLK => RXCLK,          RXCLKDIV => RXCLKDIV,          IDELAY_READY => IDELAY_READY,          RT_MANUAL_DISABLE => RT_MANUAL_DISABLE        ); 	-- Instantiate the Unit Under Test (UUT)   uut_tx: DDR_6TO1_16CHAN_RT_TX PORT MAP (          DATA_TX_P => DATA_TX_P,          DATA_TX_N => DATA_TX_N,          CLOCK_TX_P => CLOCK_TX_P,          CLOCK_TX_N => CLOCK_TX_N,          TXCLK => TXCLK,          TXCLKDIV => TXCLKDIV,          DATA_TO_OSERDES => DATA_TO_OSERDES,          RESET => RESET,          TRAINING_DONE => TRAINING_DONE        );   -- No clocks detected in port list. Replace <clock> below with    -- appropriate port name      CLK200_process :process   begin		CLK200 <= '0';		wait for (CLK200_period/2);		CLK200 <= '1';		wait for (CLK200_period/2);   end process;     TXCLK_process :process   begin		TXCLK <= '0';		wait for (TXCLK_period/2);		TXCLK <= '1';		wait for (TXCLK_period/2);   end process;		TXCLKDIV_process :process   begin		TXCLKDIV <= '0';		wait for (TXCLKDIV_period/2);		TXCLKDIV <= '1';		wait for (TXCLKDIV_period/2);   end process;		DATA_RX_P(0) <= TRANSPORT DATA_TX_P(0) after delay1 ;	DATA_RX_N(0) <= TRANSPORT DATA_TX_N(0) after delay1 ;	----------------------------------------------------	DATA_RX_P(1) <= TRANSPORT DATA_TX_P(1) after delay2 ;	DATA_RX_N(1) <= TRANSPORT DATA_TX_N(1) after delay2 ;	----------------------------------------------------	DATA_RX_P(2) <= TRANSPORT DATA_TX_P(2) after delay3 ;	DATA_RX_N(2) <= TRANSPORT DATA_TX_N(2) after delay3 ;	----------------------------------------------------	DATA_RX_P(3) <= TRANSPORT DATA_TX_P(3) after delay4 ;	DATA_RX_N(3) <= TRANSPORT DATA_TX_N(3) after delay4 ;	----------------------------------------------------	DATA_RX_P(4) <= TRANSPORT DATA_TX_P(4) after delay5 ;	DATA_RX_N(4) <= TRANSPORT DATA_TX_N(4) after delay5 ;	----------------------------------------------------	DATA_RX_P(5) <= TRANSPORT DATA_TX_P(5) after delay6 ;	DATA_RX_N(5) <= TRANSPORT DATA_TX_N(5) after delay6 ;	----------------------------------------------------	DATA_RX_P(6) <= TRANSPORT DATA_TX_P(6) after delay7 ;	DATA_RX_N(6) <= TRANSPORT DATA_TX_N(6) after delay7 ;	----------------------------------------------------	DATA_RX_P(7) <= TRANSPORT DATA_TX_P(7) after delay8 ;	DATA_RX_N(7) <= TRANSPORT DATA_TX_N(7) after delay8 ;	----------------------------------------------------	DATA_RX_P(8) <= TRANSPORT DATA_TX_P(8) after delay9 ;	DATA_RX_N(8) <= TRANSPORT DATA_TX_N(8) after delay9 ;	----------------------------------------------------	DATA_RX_P(9) <= TRANSPORT DATA_TX_P(9) after delay10;	DATA_RX_N(9) <= TRANSPORT DATA_TX_N(9) after delay10;	----------------------------------------------------	DATA_RX_P(10) <= TRANSPORT DATA_TX_P(10) after delay11 ;	DATA_RX_N(10) <= TRANSPORT DATA_TX_N(10) after delay11 ;	----------------------------------------------------	DATA_RX_P(11) <= TRANSPORT DATA_TX_P(11) after delay12 ;	DATA_RX_N(11) <= TRANSPORT DATA_TX_N(11) after delay12 ;	----------------------------------------------------	DATA_RX_P(12) <= TRANSPORT DATA_TX_P(12) after delay13 ;	DATA_RX_N(12) <= TRANSPORT DATA_TX_N(12) after delay13 ;	----------------------------------------------------	DATA_RX_P(13) <= TRANSPORT DATA_TX_P(13) after delay14 ;	DATA_RX_N(13) <= TRANSPORT DATA_TX_N(13) after delay14 ;	----------------------------------------------------	DATA_RX_P(14) <= TRANSPORT DATA_TX_P(14) after delay15 ;	DATA_RX_N(14) <= TRANSPORT DATA_TX_N(14) after delay15 ;	----------------------------------------------------	DATA_RX_P(15) <= TRANSPORT DATA_TX_P(15) after delay16 ;	DATA_RX_N(15) <= TRANSPORT DATA_TX_N(15) after delay16 ;	----------------------------------------------------	      CLOCK_RX_P <= TRANSPORT CLOCK_TX_P after 100 ns;   CLOCK_RX_N <= TRANSPORT CLOCK_TX_N after 100 ns;--	DATA_RX_P <= DATA_TX_P ;--	DATA_RX_N <= DATA_TX_N ;--   --   CLOCK_RX_P <= CLOCK_TX_P ;--   CLOCK_RX_N <= CLOCK_TX_N ;      -- Stimulus process   stim_proc: process   begin		      -- hold reset state for 1ms.      		wait for 5 us;		RESET <= '0';      IDLY_RESET <='0';      IDELAYCTRL_RESET <='0';      -- insert stimulus here       wait;   end process;END;