?? generate_icon_pro.xco
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NEWPROJECT .SETPROJECT .SET device=xc5vlx30SET flowvendor=OtherSET createndf=FalseSET formalverification=FalseSET speedgrade=-3SET removerpms=FalseSET devicefamily=virtex5SET asysymbol=FalseSET simulationfiles=structuralSET implementationfiletype=NgcSET busformat=BusFormatAngleBracketNotRippedSET designentry=VHDLSET addpads=FalseSET foundationsym=FalseSET package=ff324SET vhdlsim=TrueSET verilogsim=FalseSELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.03.aCSET number_control_ports=1CSET enable_jtag_bufg=trueCSET component_name=icon_proCSET user_scan_chain=USER1CSET use_unused_bscan=falseCSET use_ext_bscan=falseGENERATE?? 快捷鍵說明
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