////////////////////////////////////////////////////////////////////////////////// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.//////////////////////////////////////////////////////////////////////////////////   ____  ____ //  /   /\/   / // /___/  \  /    Vendor: Xilinx // \   \   \/     Version : 10.1.02//  \   \         Application : xaw2verilog//  /   /         Filename : PLL_tx.v// /___/   /\     Timestamp : 02/15/2009 20:06:25// \   \  /  \ //  \___\/\___\ ////Command: xaw2verilog -st E:\linpingping\DAC\LVDS_DDR_List_FPGA2\PLL_tx.xaw E:\linpingping\DAC\LVDS_DDR_List_FPGA2\PLL_tx//Design Name: PLL_tx//Device: xc5vfx130t-1ff1738//// Module PLL_tx// Generated by Xilinx Architecture Wizard// Written for synthesis tool: XST// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.225 ns`timescale 1ns / 1psmodule PLL_tx(CLKIN1_IN,               RST_IN,               CLKOUT0_OUT,               LOCKED_OUT,
				  CLKIN1_OUT);    input CLKIN1_IN;    input RST_IN;   output CLKOUT0_OUT;   output LOCKED_OUT;
	output CLKIN1_OUT;      wire CLKFBOUT_CLKFBIN;   wire CLKIN1_IBUFG;   wire CLKOUT0_BUF;   wire GND_BIT;   wire [4:0] GND_BUS_5;   wire [15:0] GND_BUS_16;   wire VCC_BIT;      assign GND_BIT = 0;   assign GND_BUS_5 = 5'b00000;   assign GND_BUS_16 = 16'b0000000000000000;   assign VCC_BIT = 1;
	
	assign CLKIN1_OUT=CLKIN1_IBUFG;
	   IBUFG CLKIN1_IBUFG_INST (.I(CLKIN1_IN),                             .O(CLKIN1_IBUFG));   BUFG CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF),                            .O(CLKOUT0_OUT));   PLL_ADV PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN),                          .CLKINSEL(VCC_BIT),                          .CLKIN1(CLKIN1_IBUFG),                          .CLKIN2(GND_BIT),                          .DADDR(GND_BUS_5[4:0]),                          .DCLK(GND_BIT),                          .DEN(GND_BIT),                          .DI(GND_BUS_16[15:0]),                          .DWE(GND_BIT),                          .REL(GND_BIT),                          .RST(RST_IN),                          .CLKFBDCM(),                          .CLKFBOUT(CLKFBOUT_CLKFBIN),                          .CLKOUTDCM0(),                          .CLKOUTDCM1(),                          .CLKOUTDCM2(),                          .CLKOUTDCM3(),                          .CLKOUTDCM4(),                          .CLKOUTDCM5(),                          .CLKOUT0(CLKOUT0_BUF),                          .CLKOUT1(),                          .CLKOUT2(),                          .CLKOUT3(),                          .CLKOUT4(),                          .CLKOUT5(),                          .DO(),                          .DRDY(),                          .LOCKED(LOCKED_OUT));   defparam PLL_ADV_INST.BANDWIDTH = "OPTIMIZED";   defparam PLL_ADV_INST.CLKIN1_PERIOD = 32.552;   defparam PLL_ADV_INST.CLKIN2_PERIOD = 10.000;   defparam PLL_ADV_INST.CLKOUT0_DIVIDE = 4;   defparam PLL_ADV_INST.CLKOUT1_DIVIDE = 8;   defparam PLL_ADV_INST.CLKOUT2_DIVIDE = 8;   defparam PLL_ADV_INST.CLKOUT3_DIVIDE = 8;   defparam PLL_ADV_INST.CLKOUT4_DIVIDE = 8;   defparam PLL_ADV_INST.CLKOUT5_DIVIDE = 8;   defparam PLL_ADV_INST.CLKOUT0_PHASE = 0.000;   defparam PLL_ADV_INST.CLKOUT1_PHASE = 0.000;   defparam PLL_ADV_INST.CLKOUT2_PHASE = 0.000;   defparam PLL_ADV_INST.CLKOUT3_PHASE = 0.000;   defparam PLL_ADV_INST.CLKOUT4_PHASE = 0.000;   defparam PLL_ADV_INST.CLKOUT5_PHASE = 0.000;   defparam PLL_ADV_INST.CLKOUT0_DUTY_CYCLE = 0.500;   defparam PLL_ADV_INST.CLKOUT1_DUTY_CYCLE = 0.500;   defparam PLL_ADV_INST.CLKOUT2_DUTY_CYCLE = 0.500;   defparam PLL_ADV_INST.CLKOUT3_DUTY_CYCLE = 0.500;   defparam PLL_ADV_INST.CLKOUT4_DUTY_CYCLE = 0.500;   defparam PLL_ADV_INST.CLKOUT5_DUTY_CYCLE = 0.500;   defparam PLL_ADV_INST.COMPENSATION = "SYSTEM_SYNCHRONOUS";   defparam PLL_ADV_INST.DIVCLK_DIVIDE = 1;   defparam PLL_ADV_INST.CLKFBOUT_MULT = 16;   defparam PLL_ADV_INST.CLKFBOUT_PHASE = 0.0;   defparam PLL_ADV_INST.REF_JITTER = 0.005000;endmodule