# running from command line and not in the GUI.	   puts $sMessageCmdLine   } else {	   # got a good dialog singleton	   set nTimeout 999999	   set buttonValue [$iMessageDisplay Question "Project Navigator" $sMessageGUI $hasCancel $nTimeout]	   if { $buttonValue == 2 } { ; # cancel		   return 3	   } elseif { $buttonValue == 3 } { ; # yes		   return 1	   } elseif { $buttonValue == 4 } { ; # no		   return 2	   } else { # probably timeout		   return $defaultValue	   }   }   return $defaultValue}# Call this proc to restore the ISE project.proc restore { { project_dir "" } } {   set script_file "LVDS_FPGA2.restore"   set project_file "LVDS_FPGA2.ise"   set backup_file "LVDS_FPGA2.fail"   set old_working_dir [pwd]   # Make sure a project isn't already open.   if {[IsProjectOpen]} {      ERR "The project must be closed before performing this operation."      cd $old_working_dir      return   }   # If a project directory was supplied, cd into it.   if {![IsBlank $project_dir]} {     cd $project_dir   }   # capture the project directory ... it should be CWD at this point   set project_dir [pwd]   # before proceeding detect if lock files exist and if so ask the user what to do   set proj_rootname [file rootname $project_file]   set intermediate_proj_dir [file join $project_dir ${proj_rootname}_xdb]   set proj_temp_dir [file join $intermediate_proj_dir "projtemp"]   set repo_temp_dir [file join $proj_temp_dir $project_file]   set new_lock_file [file join $proj_temp_dir ${project_file}.lock]   set old_lock_file [GetProjectLockFile $project_file]   set bLockFilesExist 0   # see if any lock files are there   if {[file exists $new_lock_file] || ![IsBlank "$old_lock_file" ] } {      set bLockFilesExist 1   }      # if lock file(s) are found ask the user what to do   if { $bLockFilesExist == 1 } {       set lockFileMsgGUI "The project to be restored appears to be locked. Remove Lock and continue the restore project process ?"       set lockFileMsgCmdLine "The project to be restored appears to be locked. Please remove the lock file \"$new_lock_file\" and try the restore process again."       set answer [dpm_DisplayQuestionDialog $lockFileMsgGUI $lockFileMsgCmdLine 2]      if { $answer == 1 } {         # remove the lock file(s) and the repo temo dir, if present         # remove the new style lock file if it exists         if {[file exists $new_lock_file]} {            INFO "Removing lock file \"$new_lock_file\"."            file delete -force $new_lock_file         }         # remove the old style lock file if it exists         if {[file exists $old_lock_file]} {            INFO "Removing lock file \"$old_lock_file\"."            file delete -force $old_lock_file         }         # remove the temp proj dir if it exists         if {[file exists $repo_temp_dir]} {            INFO "Removing old temporary project directory \"$repo_temp_dir\"."            file delete -force $repo_temp_dir         }      } else {         # the user answered 'no' so exist without doing anything         INFO "Exiting without restoring project."         return      }   }      # Backup this script because it will be overwritten the next time   # the project is saved, which happens right after it is created!   file copy -force "$script_file" "${script_file}.last"   # Back up the project.   set wasBackedUp [ BackUpProject "$project_file" "$backup_file" ]   # Remove the project file, so that it can be recreated, since the old.   # is presumably corrupted and can no longer be opened.   OnFail [ RemoveProject "$project_file" ] {      cd $old_working_dir      return   }   # Open the project.   HandleException {      set iProjHelper [ OpenFacilProject "$project_file"]   } "A problem occurred while creating the project \"$project_file\"."   if {$iProjHelper == 0} {      cd $old_working_dir      return   }   INFO "Recreating project \"$project_file\"."  set project_settings {      "PROP_DevFamily" "Virtex5"     "PROP_DevDevice" "xc5vfx130t"     "PROP_DevPackage" "ff1738"     "PROP_DevSpeed" "-1"     "PROP_Top_Level_Module_Type" "HDL"     "PROP_Synthesis_Tool" "XST (VHDL/Verilog)"     "PROP_Simulator" "Modelsim-SE Mixed"     "PROP_PreferredLanguage" "Verilog"     "PROP_Enable_Message_Capture" "true"     "PROP_Enable_Message_Filtering" "false"     "PROP_Enable_Incremental_Messaging" "false"     }  HandleException {    RestoreProjectSettings $iProjHelper $project_settings   } "A problem occured while restoring project settings."  set user_files {       "DDR_TX.v"       "DDR_TX_TEST.v"       "DDR_TX_TOP.v"       "DDR_TX_UCF.ucf"       "TB_TX_RX.v"}  HandleException {    AddUserFiles $iProjHelper $user_files  } "A problem occured while restoring user files."  set imported_files {       "DDR_TX_TEST_guide.ncd"}  set origination 2  HandleException {    AddImportedFiles $iProjHelper $imported_files $origination  } "A problem occured while restoring imported files."  set process_props {       "A" "" "" "" "PROPEXT_xilxMapGenInputK_virtex5" "6"       "A" "" "" "" "PROPEXT_xilxMapPackRegInto_virtex5" "Off"       "A" "" "" "" "PROPEXT_xilxPARstrat_virtex5" "Route Only"       "A" "" "" "" "PROPEXT_xilxSynthAddBufg_virtex5" "32"       "A" "" "" "" "PROPEXT_xilxSynthMaxFanout_virtex5" "100000"       "A" "" "" "" "PROPEXT_xstUseClockEnable_virtex5" "Auto"       "A" "" "" "" "PROPEXT_xstUseSyncReset_virtex5" "Auto"       "A" "" "" "" "PROPEXT_xstUseSyncSet_virtex5" "Auto"       "A" "" "" "" "PROP_AutoGenFile" "false"       "A" "" "" "" "PROP_BehavioralSimTop" "Module|TB_TX_RX"       "A" "" "" "" "PROP_CPLDFitkeepio" "false"       "A" "" "" "" "PROP_CompxlibAbelLib" "true"       "A" "" "" "" "PROP_CompxlibCPLDDetLib" "true"       "A" "" "" "" "PROP_CompxlibOtherCompxlibOpts" ""       "A" "" "" "" "PROP_CompxlibOutputDir" "$XILINX/<language>/<simulator>"       "A" "" "" "" "PROP_CompxlibOverwriteLib" "Overwrite"       "A" "" "" "" "PROP_CompxlibSimPrimatives" "true"       "A" "" "" "" "PROP_CompxlibXlnxCoreLib" "true"       "A" "" "" "" "PROP_ConstFileAddOption" "true"       "A" "" "" "" "PROP_ConstFileName" ""       "A" "" "" "" "PROP_CorgenRegenCore" "Under Current Project Setting"       "A" "" "" "" "PROP_CurrentFloorplanFile" ""       "A" "" "" "" "PROP_DefaultTBName" "Default"       "A" "" "" "" "PROP_DesignName" "LVDS_FPGA2"       "A" "" "" "" "PROP_Dummy" "dum1"       "A" "" "" "" "PROP_EnableWYSIWYG" "None"       "A" "" "" "" "PROP_Enable_Incremental_Messaging" "false"       "A" "" "" "" "PROP_Enable_Message_Capture" "true"       "A" "" "" "" "PROP_Enable_Message_Filtering" "false"       "A" "" "" "" "PROP_FitterReportFormat" "HTML"       "A" "" "" "" "PROP_FlowDebugLevel" "0"       "A" "" "" "" "PROP_FunctionBlockInputLimit" "38"       "A" "" "" "" "PROP_HierarchicalProjectType" "N/A"       "A" "" "" "" "PROP_ISimLibSearchOrderFile" ""       "A" "" "" "" "PROP_ISimOtherCompilerOptions_behav" ""       "A" "" "" "" "PROP_ISimOtherCompilerOptions_fit" ""       "A" "" "" "" "PROP_ISimOtherCompilerOptions_par" ""       "A" "" "" "" "PROP_ISimSDFTimingToBeRead" "Setup Time"       "A" "" "" "" "PROP_ISimSpecifyDefMacroAndValueChkSyntax" ""       "A" "" "" "" "PROP_ISimSpecifySearchDirectoryChkSyntax" ""       "A" "" "" "" "PROP_ISimUseCustomCompilationOrder" "false"       "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tb" "false"       "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tbw" "false"       "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_gen_tbw" "false"       "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_launch" "false"       "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tb" "false"       "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tbw" "false"       "A" "" "" "" "PROP_ISimUutInstName" "UUT"       "A" "" "" "" "PROP_ImpactProjectFile" "Default"       "A" "" "" "" "PROP_LastAppliedGoal" "Balanced"       "A" "" "" "" "PROP_LastAppliedStrategy" "Xilinx Default (unlocked)"       "A" "" "" "" "PROP_LastUnlockStatus" "false"       "A" "" "" "" "PROP_LoadPostTrceTSIFile" "false"       "A" "" "" "" "PROP_MSimSDFTimingToBeRead" "Setup Time"       "A" "" "" "" "PROP_MapEffortLevel_virtex5" "High"       "A" "" "" "" "PROP_MapGlobalOptimization" "false"       "A" "" "" "" "PROP_MapLUTCombining_virtex5" "Off"       "A" "" "" "" "PROP_MapLogicOptimization_virtex5" "false"       "A" "" "" "" "PROP_MapPlacerCostTable_virtex5" "1"       "A" "" "" "" "PROP_MapPowerReduction_virtex5" "false"       "A" "" "" "" "PROP_MapRegDuplication_virtex5" "false"       "A" "" "" "" "PROP_ModelSimUseConfigName" "false"       "A" "" "" "" "PROP_OverwriteSym" "false"       "A" "" "" "" "PROP_Parse_Target" "synthesis"       "A" "" "" "" "PROP_PartitionCreateDelete" ""       "A" "" "" "" "PROP_PartitionForcePlacement" ""       "A" "" "" "" "PROP_PartitionForceSynth" ""       "A" "" "" "" "PROP_PartitionForceTranslate" ""       "A" "" "" "" "PROP_PlsClockEnable" "true"       "A" "" "" "" "PROP_PostFitSimTop" ""       "A" "" "" "" "PROP_PostMapSimTop" "Module|TB_TX_RX"       "A" "" "" "" "PROP_PostParSimTop" "Module|TB_TX_RX"       "A" "" "" "" "PROP_PostSynthSimTop" "Module|TB_TX_RX"       "A" "" "" "" "PROP_PostTrceFastPath" "false"       "A" "" "" "" "PROP_PostTrceGenDatasheet" "true"       "A" "" "" "" "PROP_PostTrceGenTimegroups" "false"       "A" "" "" "" "PROP_PostXlateSimTop" "Module|TB_TX_RX"       "A" "" "" "" "PROP_PreTrceFastPath" "false"       "A" "" "" "" "PROP_PreTrceGenDatasheet" "true"       "A" "" "" "" "PROP_PreTrceGenTimegroups" "false"       "A" "" "" "" "PROP_PreTrceTSIFile" ""       "A" "" "" "" "PROP_PrecAddIOPads" "true"       "A" "" "" "" "PROP_PrecAdvFsmOptimization" "true"       "A" "" "" "" "PROP_PrecArrayBoundsCheck" "false"       "A" "" "" "" "PROP_PrecCreateUcfFromRtlConstraints" "false"       "A" "" "" "" "PROP_PrecEdif" "true"       "A" "" "" "" "PROP_PrecFsmEncoding" "Auto"       "A" "" "" "" "PROP_PrecFullCase" "false"       "A" "" "" "" "PROP_PrecInputSdcFile" ""       "A" "" "" "" "PROP_PrecOutputFileBase" ""       "A" "" "" "" "PROP_PrecParallelCase" "false"       "A" "" "" "" "PROP_PrecResourceSharing" "true"       "A" "" "" "" "PROP_PrecRptCriticalPaths" "true"       "A" "" "" "" "PROP_PrecRptMissingConstraints" "false"       "A" "" "" "" "PROP_PrecRptTimingSummary" "true"       "A" "" "" "" "PROP_PrecRptTimingViolations" "true"       "A" "" "" "" "PROP_PrecRptclockFreq" "true"       "A" "" "" "" "PROP_PrecRunRetiming" "false"       "A" "" "" "" "PROP_PrecShowClockDomainCrossing" "false"       "A" "" "" "" "PROP_PrecShowNetFanOut" "true"       "A" "" "" "" "PROP_PrecTranSetResetToLatches" "true"       "A" "" "" "" "PROP_PrecUseSafeFsm" "false"       "A" "" "" "" "PROP_PrecVerilog" "false"       "A" "" "" "" "PROP_PrecVhdl" "false"       "A" "" "" "" "PROP_PrecVhdlSyntax" "VHDL 93"       "A" "" "" "" "PROP_ProjectGeneratorType" "ProjNav"       "A" "" "" "" "PROP_ReduceControlSets_virtex5" "No"       "A" "" "" "" "PROP_SimDo" "true"       "A" "" "" "" "PROP_SimModelGenerateTestbenchFile" "false"       "A" "" "" "" "PROP_SimModelInsertBuffersPulseSwallow" "false"       "A" "" "" "" "PROP_SimModelOtherNetgenOpts" ""       "A" "" "" "" "PROP_SimModelRetainHierarchy" "true"       "A" "" "" "" "PROP_SimUseCustom_behav" "false"       "A" "" "" "" "PROP_SimUseCustom_launchMSim" "false"       "A" "" "" "" "PROP_SimUseCustom_postMap" "false"       "A" "" "" "" "PROP_SimUseCustom_postPar" "false"       "A" "" "" "" "PROP_SimUseCustom_postXlate" "false"       "A" "" "" "" "PROP_SimUserCompileList_launchMSim" ""       "A" "" "" "" "PROP_StartImpView" ""       "A" "" "" "" "PROP_StopImpView" "AbstractSynthesis"       "A" "" "" "" "PROP_SynthCaseImplStyle" "None"       "A" "" "" "" "PROP_SynthDecoderExtract" "true"       "A" "" "" "" "PROP_SynthDisableIOInsertion" "false"       "A" "" "" "" "PROP_SynthEncoderExtract" "Yes"       "A" "" "" "" "PROP_SynthEnumEncoding" "default"       "A" "" "" "" "PROP_SynthExtractMux" "Yes"       "A" "" "" "" "PROP_SynthExtractRAM" "true"       "A" "" "" "" "PROP_SynthExtractROM" "true"       "A" "" "" "" "PROP_SynthFanout" "100"       "A" "" "" "" "PROP_SynthFsmEncode" "Auto"       "A" "" "" "" "PROP_SynthLogicalShifterExtract" "true"       "A" "" "" "" "PROP_SynthModular" "false"       "A" "" "" "" "PROP_SynthMultStyle" "LUT"       "A" "" "" "" "PROP_SynthNumCriticalPaths" "0"       "A" "" "" "" "PROP_SynthNumStartEndPoints" "0"       "A" "" "" "" "PROP_SynthOpt" "Speed"       "A" "" "" "" "PROP_SynthOptEffort" "Normal"       "A" "" "" "" "PROP_SynthPipelining" "true"       "A" "" "" "" "PROP_SynthProcBound" "true"       "A" "" "" "" "PROP_SynthResSharing" "true"       "A" "" "" "" "PROP_SynthResourceSharing" "true"       "A" "" "" "" "PROP_SynthRetiming" "false"       "A" "" "" "" "PROP_SynthShiftRegExtract" "true"       "A" "" "" "" "PROP_SynthSymbolicFsm" "true"       "A" "" "" "" "PROP_SynthTop" "Module|DDR_TX_TEST"       "A" "" "" "" "PROP_SynthUseFsmExplorerData" "false"       "A" "" "" "" "PROP_SynthXORCollapse" "true"       "A" "" "" "" "PROP_ToolPathChipscope" ""       "A" "" "" "" "PROP_ToolPathModelSim" ""       "A" "" "" "" "PROP_ToolPathPrecision" ""       "A" "" "" "" "PROP_ToolPathSynplify" ""       "A" "" "" "" "PROP_ToolPathSynplifyPro" ""       "A" "" "" "" "PROP_Top_Level_Module_Type" "HDL"       "A" "" "" "" "PROP_UseDataGate" "true"       "A" "" "" "" "PROP_UseSmartGuide" "false"       "A" "" "" "" "PROP_UserBrowsedStrategyFiles" ""       "A" "" "" "" "PROP_UserConstraintEditorPreference" "Constraints Editor"       "A" "" "" "" "PROP_UserEditorCustomSetting" ""       "A" "" "" "" "PROP_UserEditorPreference" "ISE Text Editor"       "A" "" "" "" "PROP_Verilog2001" "true"       "A" "" "" "" "PROP_VirtexSynthAutoConstrain" "true"       "A" "" "" "" "PROP_WriteVHDLNetlist" "false"       "A" "" "" "" "PROP_WriteVendorConstFile" "true"       "A" "" "" "" "PROP_WriteVerilogNetlist" "false"       "A" "" "" "" "PROP_XPORTInpFileName" ""       "A" "" "" "" "PROP_XPORTInpFileType" "ABEL"       "A" "" "" "" "PROP_XPORTOutFileType" "VHDL"       "A" "" "" "" "PROP_XPORTlistInpFiles" "false"       "A" "" "" "" "PROP_XPowerOptInputTclScript" ""       "A" "" "" "" "PROP_XPowerOptLoadPCFFile" "Default"       "A" "" "" "" "PROP_XPowerOptLoadVCDFile" "Default"       "A" "" "" "" "PROP_XPowerOptLoadXMLFile" "Default"       "A" "" "" "" "PROP_XPowerOptOutputFile" "Default"       "A" "" "" "" "PROP_XPowerOptVerboseRpt" "false"       "A" "" "" "" "PROP_XPowerOtherXPowerOpts" ""       "A" "" "" "" "PROP_XplorerMode" "Off"       "A" "" "" "" "PROP_bitgen_otherCmdLineOptions" ""       "A" "" "" "" "PROP_bitgen_otherCmdLineOptions_virtex5" ""       "A" "" "" "" "PROP_cpldBestFit" "false"       "A" "" "" "" "PROP_cpldfitHDLeqStyle" "Source"       "A" "" "" "" "PROP_cpldfit_otherCmdLineOptions" ""       "A" "" "" "" "PROP_fitGenSimModel" "false"       "A" "" "" "" "PROP_hprep6_autosig" "false"       "A" "" "" "" "PROP_hprep6_otherCmdLineOptions" ""       "A" "" "" "" "PROP_ibiswriterGeneratePackageParasitics" "false"       "A" "" "" "" "PROP_ibiswriterShowAllModels" "false"       "A" "" "" "" "PROP_isimCompileForHdlDebug" "true"       "A" "" "" "" "PROP_isimIncreCompilation" "true"       "A" "" "" "" "PROP_isimSpecifyDefMacroAndValue" ""       "A" "" "" "" "PROP_isimSpecifySearchDirectory" ""       "A" "" "" "" "PROP_isimValueRangeCheck" "false"       "A" "" "" "" "PROP_lockPinsUcfFile" ""       "A" "" "" "" "PROP_mapIgnoreTimingConstraints" "false"       "A" "" "" "" "PROP_mapTimingAnalyzerLoadDesign" "true"       "A" "" "" "" "PROP_mapUseRLOCConstraints" "true"       "A" "" "" "" "PROP_map_otherCmdLineOptions" ""       "A" "" "" "" "PROP_mpprRsltToCopy" ""       "A" "" "" "" "PROP_mpprViewPadRptsForAllRslt" "true"       "A" "" "" "" "PROP_mpprViewParRptsForAllRslt" "true"       "A" "" "" "" "PROP_ngdbuildUseLOCConstraints" "true"       "A" "" "" "" "PROP_ngdbuild_otherCmdLineOptions" ""       "A" "" "" "" "PROP_parIgnoreTimingConstraints" "false"       "A" "" "" "" "PROP_parTimingAnalyzerLoadDesign" "true"       "A" "" "" "" "PROP_par_otherCmdLineOptions" ""       "A" "" "" "" "PROP_primeCorrelateOutput" "false"       "A" "" "" "" "PROP_primeFlatternOutputNetlist" "false"       "A" "" "" "" "PROP_primeTopLevelModule" ""       "A" "" "" "" "PROP_primetimeBlockRamData" ""       "A" "" "" "" "PROP_taengine_otherCmdLineOptions" ""       "A" "" "" "" "PROP_usedsp48_virtex5" "Auto"       "A" "" "" "" "PROP_xcpldFitDesInit" "Low"       "A" "" "" "" "PROP_xcpldFitDesInputLmt_xbr" "32"       "A" "" "" "" "PROP_xcpldFitDesMultiLogicOpt" "true"       "A" "" "" "" "PROP_xcpldFitDesSlew" "Fast"       "A" "" "" "" "PROP_xcpldFitDesTimingCst" "true"       "A" "" "" "" "PROP_xcpldFitDesTriMode" "Keeper"       "A" "" "" "" "PROP_xcpldFitDesUnused" "Keeper"       "A" "" "" "" "PROP_xcpldFitDesVolt" "LVCMOS18"       "A" "" "" "" "PROP_xcpldFitTemplate_xpla3" "Optimize Density"