"A" "" "" "" "PROP_xcpldFittimRptOption" "Summary"       "A" "" "" "" "PROP_xcpldUseGlobalClocks" "true"       "A" "" "" "" "PROP_xcpldUseGlobalOutputEnables" "true"       "A" "" "" "" "PROP_xcpldUseGlobalSetReset" "true"       "A" "" "" "" "PROP_xcpldUseLocConst" "Always"       "A" "" "" "" "PROP_xilxBitgCfg_BPI_Page_Size_virtex5" "1"       "A" "" "" "" "PROP_xilxBitgCfg_Busy_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_Clk" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_Clk_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_Code" "0xFFFFFFFF"       "A" "" "" "" "PROP_xilxBitgCfg_Code_virtex5" "0xFFFFFFFF"       "A" "" "" "" "PROP_xilxBitgCfg_Cs_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_DCIUpdateMode_virtex5" "As Required"       "A" "" "" "" "PROP_xilxBitgCfg_Din_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_Done" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_Done_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ASCIIFile" "false"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ASCIIFile_virtex5" "false"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BinaryFile" "false"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BinaryFile_virtex5" "false"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BitFile" "true"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BitFile_virtex5" "true"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_Compress" "false"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_Compress_virtex5" "false"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC" "true"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC_virtex5" "true"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_EnableCRC_virtex5" "true"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel0" "11111"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel1" "11111"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel2" "11111"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel3" "11111"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_virtex5" "false"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr" "false"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack" "false"       "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack_virtex5" "false"       "A" "" "" "" "PROP_xilxBitgCfg_Init_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_M0" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_M0_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_M1" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_M1_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_M2" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_M2_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_Pgm" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_Pgm_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_PwrDown_Safe_Temp_virtex5" "false"       "A" "" "" "" "PROP_xilxBitgCfg_Rate" "4"       "A" "" "" "" "PROP_xilxBitgCfg_Rate_virtex5" "2"       "A" "" "" "" "PROP_xilxBitgCfg_Rdwr_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_Retain_Config_Status_Register_Values_virtex5" "true"       "A" "" "" "" "PROP_xilxBitgCfg_SelectMAP_Abort_Sequence_virtex5" "Enable"       "A" "" "" "" "PROP_xilxBitgCfg_TCK" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_TCK_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_TDI" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_TDI_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_TDO" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_TDO_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_TMS" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_TMS_virtex5" "Pull Up"       "A" "" "" "" "PROP_xilxBitgCfg_Unused" "Pull Down"       "A" "" "" "" "PROP_xilxBitgCfg_Unused_virtex5" "Pull Down"       "A" "" "" "" "PROP_xilxBitgReadBk_Sec" "Enable Readback and Reconfiguration"       "A" "" "" "" "PROP_xilxBitgReadBk_Sec_virtex5" "Enable Readback and Reconfiguration"       "A" "" "" "" "PROP_xilxBitgStart_Clk" "CCLK"       "A" "" "" "" "PROP_xilxBitgStart_Clk_Done" "Default (4)"       "A" "" "" "" "PROP_xilxBitgStart_Clk_Done_virtex5" "Default (4)"       "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone" "false"       "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone_virtex5" "false"       "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut" "Default (5)"       "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut_virtex5" "Default (5)"       "A" "" "" "" "PROP_xilxBitgStart_Clk_MatchCycle_virtex5" "Auto"       "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL" "Default (NoWait)"       "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL_virtex5" "Default (NoWait)"       "A" "" "" "" "PROP_xilxBitgStart_Clk_RelSet" "Default (6)"       "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn" "Default (6)"       "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn_virtex5" "Default (6)"       "A" "" "" "" "PROP_xilxBitgStart_Clk_virtex5" "CCLK"       "A" "" "" "" "PROP_xilxBitgStart_IntDone" "false"       "A" "" "" "" "PROP_xilxBitgStart_IntDone_virtex5" "false"       "A" "" "" "" "PROP_xilxMapAllowLogicOpt" "false"       "A" "" "" "" "PROP_xilxMapCoverMode" "Area"       "A" "" "" "" "PROP_xilxMapDisableRegOrdering" "false"       "A" "" "" "" "PROP_xilxMapMaxCompression_virtex5" "false"       "A" "" "" "" "PROP_xilxMapReplicateLogic" "true"       "A" "" "" "" "PROP_xilxMapReportDetail" "false"       "A" "" "" "" "PROP_xilxMapSliceLogicInUnusedBRAMs" "false"       "A" "" "" "" "PROP_xilxMapTimingDrivenPacking" "false"       "A" "" "" "" "PROP_xilxMapTrimUnconnSig" "true"       "A" "" "" "" "PROP_xilxNgdbldIOPads" "false"       "A" "" "" "" "PROP_xilxNgdbldMacro" ""       "A" "" "" "" "PROP_xilxNgdbldNTType" "Timestamp"       "A" "" "" "" "PROP_xilxNgdbldUR" ""       "A" "" "" "" "PROP_xilxNgdbldUnexpBlks" "false"       "A" "" "" "" "PROP_xilxNgdbld_AUL" "false"       "A" "" "" "" "PROP_xilxPARplacerCostTable" "1"       "A" "" "" "" "PROP_xilxPARplacerEffortLevel" "None"       "A" "" "" "" "PROP_xilxPARrouterEffortLevel" "None"       "A" "" "" "" "PROP_xilxPARuseBondedIO" "false"       "A" "" "" "" "PROP_xilxPostTrceAdvAna" "false"       "A" "" "" "" "PROP_xilxPostTrceEndpointPath" ""       "A" "" "" "" "PROP_xilxPostTrceRpt" "Verbose Report"       "A" "" "" "" "PROP_xilxPostTrceRptLimit" "3"       "A" "" "" "" "PROP_xilxPostTrceStamp" ""       "A" "" "" "" "PROP_xilxPostTrceTSIFile" ""       "A" "" "" "" "PROP_xilxPostTrceUncovPath" ""       "A" "" "" "" "PROP_xilxPreTrceAdvAna" "false"       "A" "" "" "" "PROP_xilxPreTrceEndpointPath" ""       "A" "" "" "" "PROP_xilxPreTrceRpt" "Verbose Report"       "A" "" "" "" "PROP_xilxPreTrceRptLimit" "3"       "A" "" "" "" "PROP_xilxPreTrceUncovPath" ""       "A" "" "" "" "PROP_xilxSynthAddIObuf" "true"       "A" "" "" "" "PROP_xilxSynthGlobOpt" "AllClockNets"       "A" "" "" "" "PROP_xilxSynthKeepHierarchy" "No"       "A" "" "" "" "PROP_xilxSynthKeepHierarchy_CPLD" "Yes"       "A" "" "" "" "PROP_xilxSynthMacroPreserve" "true"       "A" "" "" "" "PROP_xilxSynthRegBalancing" "No"       "A" "" "" "" "PROP_xilxSynthRegDuplication" "true"       "A" "" "" "" "PROP_xilxSynthXORPreserve" "true"       "A" "" "" "" "PROP_xilxTriStateBuffTXMode" "Off"       "A" "" "" "" "PROP_xstAsynToSync" "false"       "A" "" "" "" "PROP_xstAutoBRAMPacking" "false"       "A" "" "" "" "PROP_xstBRAMUtilRatio" "100"       "A" "" "" "" "PROP_xstBusDelimiter" "<>"       "A" "" "" "" "PROP_xstCase" "Maintain"       "A" "" "" "" "PROP_xstCoresSearchDir" ""       "A" "" "" "" "PROP_xstCrossClockAnalysis" "false"       "A" "" "" "" "PROP_xstDSPUtilRatio_virtex5" "100"       "A" "" "" "" "PROP_xstEquivRegRemoval" "true"       "A" "" "" "" "PROP_xstFsmStyle" "LUT"       "A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes"       "A" "" "" "" "PROP_xstGenericsParameters" ""       "A" "" "" "" "PROP_xstHierarchySeparator" "/"       "A" "" "" "" "PROP_xstIniFile" ""       "A" "" "" "" "PROP_xstLUTCombining_virtex5" "No"       "A" "" "" "" "PROP_xstLibSearchOrder" ""       "A" "" "" "" "PROP_xstNetlistHierarchy" "As Optimized"       "A" "" "" "" "PROP_xstOptimizeInsPrimtives" "false"       "A" "" "" "" "PROP_xstPackIORegister" "Auto"       "A" "" "" "" "PROP_xstPowerOptimization_virtex5" "false"       "A" "" "" "" "PROP_xstReadCores" "true"       "A" "" "" "" "PROP_xstSlicePacking" "true"       "A" "" "" "" "PROP_xstSliceUtilRatio" "100"       "A" "" "" "" "PROP_xstTristate2Logic" "Yes"       "A" "" "" "" "PROP_xstUseSynthConstFile" "true"       "A" "" "" "" "PROP_xstUserCompileList" ""       "A" "" "" "" "PROP_xstVeriIncludeDir_Global" ""       "A" "" "" "" "PROP_xstVerilog2001" "true"       "A" "" "" "" "PROP_xstVerilogMacros" ""       "A" "" "" "" "PROP_xstWorkDir" "./xst"       "A" "" "" "" "PROP_xstWriteTimingConstraints" "false"       "A" "" "" "" "PROP_xst_otherCmdLineOptions" ""       "A" "" "" "PROP_SteCreatedBy" "PROP_SteCreatedBy" ""       "B" "" "" "" "PROPEXT_SynthFrequencySyn_virtex5" "0.0"       "B" "" "" "" "PROPEXT_mapTimingMode_virtex5" "Performance Evaluation"       "B" "" "" "" "PROPEXT_parGenAsyDlyRpt_virtex5" "false"       "B" "" "" "" "PROPEXT_parGenClkRegionRpt_virtex5" "false"       "B" "" "" "" "PROPEXT_parGenSimModel_virtex5" "false"       "B" "" "" "" "PROPEXT_parGenTimingRpt_virtex5" "true"       "B" "" "" "" "PROPEXT_parMpprNodelistFile_virtex5" ""       "B" "" "" "" "PROPEXT_parMpprParIterations_virtex5" "3"       "B" "" "" "" "PROPEXT_parMpprResultsDirectory_virtex5" ""       "B" "" "" "" "PROPEXT_parMpprResultsToSave_virtex5" ""       "B" "" "" "" "PROPEXT_parPowerReduction_virtex5" "false"       "B" "" "" "" "PROPEXT_xilxPAReffortLevel_virtex5" "Standard"       "B" "" "" "" "PROP_DevFamily" "Virtex5"       "B" "" "" "" "PROP_FitterOptimization_xpla3" "Density"       "B" "" "" "" "PROP_ISimCustomCompilationOrderFile" ""       "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tb" ""       "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tbw" ""       "B" "" "" "" "PROP_ISimCustomSimCmdFileName_gen_tbw" ""       "B" "" "" "" "PROP_ISimCustomSimCmdFileName_launch" ""       "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tb" ""       "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tbw" ""       "B" "" "" "" "PROP_ISimGenVCDFile_par_tb" "false"       "B" "" "" "" "PROP_ISimGenVCDFile_par_tbw" "false"       "B" "" "" "" "PROP_ISimSimulationRun_behav_tb" "true"       "B" "" "" "" "PROP_ISimSimulationRun_behav_tbw" "true"       "B" "" "" "" "PROP_ISimSimulationRun_par_tb" "true"       "B" "" "" "" "PROP_ISimSimulationRun_par_tbw" "true"       "B" "" "" "" "PROP_MapEquivalentRegisterRemoval" "true"       "B" "" "" "" "PROP_MapExtraEffort_virtex5" "None"       "B" "" "" "" "PROP_MapPowerActivityFile_virtex5" ""       "B" "" "" "" "PROP_MapPowerReduction" "false"       "B" "" "" "" "PROP_MapRetiming" "false"       "B" "" "" "" "PROP_ModelSimConfigName" "Default"       "B" "" "" "" "PROP_ModelSimDataWin" "false"       "B" "" "" "" "PROP_ModelSimListWin" "false"       "B" "" "" "" "PROP_ModelSimProcWin" "false"       "B" "" "" "" "PROP_ModelSimSignalWin" "true"       "B" "" "" "" "PROP_ModelSimSimRes" "Default (1 ps)"       "B" "" "" "" "PROP_ModelSimSimRunTime_tb" "1000ns"       "B" "" "" "" "PROP_ModelSimSimRunTime_tbw" "1000ns"       "B" "" "" "" "PROP_ModelSimSourceWin" "false"       "B" "" "" "" "PROP_ModelSimStructWin" "true"       "B" "" "" "" "PROP_ModelSimUutInstName_postFit" "UUT"       "B" "" "" "" "PROP_ModelSimUutInstName_postMap" "UUT"       "B" "" "" "" "PROP_ModelSimUutInstName_postPar" "UUT"       "B" "" "" "" "PROP_ModelSimVarsWin" "false"       "B" "" "" "" "PROP_ModelSimWaveWin" "true"       "B" "" "" "" "PROP_PrecNumOfCriticalPaths" "1"       "B" "" "" "" "PROP_PrecNumOfSumPaths" "10"       "B" "" "" "" "PROP_SimCustom_behav" ""       "B" "" "" "" "PROP_SimCustom_launchMSim" ""       "B" "" "" "" "PROP_SimCustom_postMap" ""       "B" "" "" "" "PROP_SimCustom_postPar" ""       "B" "" "" "" "PROP_SimCustom_postXlate" ""       "B" "" "" "" "PROP_SimGenVcdFile" "false"       "B" "" "" "" "PROP_SimModelRenTopLevInstTo" "UUT"       "B" "" "" "" "PROP_SimSyntax" "93"       "B" "" "" "" "PROP_SimUseExpDeclOnly" "true"       "B" "" "" "" "PROP_SimUserCompileList_behav" ""       "B" "" "" "" "PROP_Simulator" "Modelsim-SE Mixed"       "B" "" "" "" "PROP_SmartGuideFileName" "DDR_TX_TEST_guide.ncd"       "B" "" "" "" "PROP_SynthConstraintsFile" ""       "B" "" "" "" "PROP_SynthMuxStyle" "Auto"       "B" "" "" "" "PROP_SynthRAMStyle" "Auto"       "B" "" "" "" "PROP_XPowerOptAdvancedVerboseRpt" "false"       "B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000"       "B" "" "" "" "PROP_XplorerEnableRetiming" "true"       "B" "" "" "" "PROP_XplorerNumIterations" "7"       "B" "" "" "" "PROP_XplorerOtherCmdLineOptions" ""       "B" "" "" "" "PROP_XplorerRunType" "Yes"       "B" "" "" "" "PROP_XplorerWarnToBackup" "true"       "B" "" "" "" "PROP_bitgen_Encrypt_Encrypt_virtex5" "false"       "B" "" "" "" "PROP_impactBaud" "None"       "B" "" "" "" "PROP_impactPort" "Auto - default"       "B" "" "" "" "PROP_mpprViewPadRptForSelRslt" ""       "B" "" "" "" "PROP_mpprViewParRptForSelRslt" ""       "B" "" "" "" "PROP_parTimingMode" "Performance Evaluation"       "B" "" "" "" "PROP_vcom_otherCmdLineOptions" ""       "B" "" "" "" "PROP_vlog_otherCmdLineOptions" ""       "B" "" "" "" "PROP_vsim_otherCmdLineOptions" ""       "B" "" "" "" "PROP_xcpldFitDesInReg_xbr" "true"       "B" "" "" "" "PROP_xcpldFitDesPtermLmt_xbr" "28"       "B" "" "" "" "PROP_xilxBitgCfg_BPI_First_Read_Cycle_virtex5" "2"       "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr" "false"       "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr_virtex5" "false"       "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile" "false"       "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex5" "false"       "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile" "false"       "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile_virtex5" "false"       "B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr" "false"       "B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr_virtex5" "false"       "B" "" "" "" "PROP_xilxMapPackfactor" "100"       "B" "" "" "" "PROP_xstMoveFirstFfStage" "true"       "B" "" "" "" "PROP_xstMoveLastFfStage" "true"       "B" "" "" "" "PROP_xstROMStyle" "Auto"       "B" "" "" "" "PROP_xstSafeImplement" "No"       "C" "" "" "" "PROPEXT_parPowerActivityFile_virtex5" ""       "C" "" "" "" "PROPEXT_xilxPARextraEffortLevel_virtex5" "None"       "C" "" "" "" "PROP_CompxlibLang" "All"       "C" "" "" "" "PROP_CompxlibSimPath" "d:/Modeltech_6.1f/win32"       "C" "" "" "" "PROP_CompxlibSmartModels" "true"       "C" "" "" "" "PROP_CompxlibUpdateIniForSmartModel" "false"       "C" "" "" "" "PROP_DevDevice" "xc5vfx130t"       "C" "" "" "" "PROP_DevFamilyPMName" "virtex5"       "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tb" "1000 ns"       "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tbw" "1000 ns"       "C" "" "" "" "PROP_ISimSimulationRunTime_par_tb" "1000 ns"       "C" "" "" "" "PROP_ISimSimulationRunTime_par_tbw" "1000 ns"       "C" "" "" "" "PROP_ISimVCDFileName_par_tb" "xpower.vcd"       "C" "" "" "" "PROP_ISimVCDFileName_par_tbw" "xpower.vcd"       "C" "" "" "" "PROP_MapPowerActivityFile" ""       "C" "" "" "" "PROP_SimModelGenMultiHierFile" "false"       "C" "" "" "" "PROP_bitgen_Encrypt_key0_virtex5" ""       "C" "" "" "" "PROP_bitgen_Encrypt_keyFile_virtex5" ""       "C" "" "" "" "PROP_xilxBitgCfg_Fallback_Reconfig_virtex5" "Enable"       "D" "" "" "" "PROP_CompxlibUni9000Lib" "true"       "D" "" "" "" "PROP_CompxlibUniSimLib" "true"       "D" "" "" "" "PROP_DevPackage" "ff1738"       "D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)"       "E" "" "" "" "PROP_DevSpeed" "-1"       "E" "" "" "" "PROP_PreferredLanguage" "Verilog"       "F" "" "" "" "PROP_ChangeDevSpeed" "-1"       "F" "" "" "" "PROP_HdlTemplateLang" "Verilog"       "F" "" "" "" "PROP_SimModelTarget" "Verilog"       "F" "" "" "" "PROP_coregenFuncModelTargetLang" "Verilog"       "F" "" "" "" "PROP_hdlInstTempTargetLang" "Verilog"       "F" "" "" "" "PROP_schFuncModelTargetLang" "Verilog"       "F" "" "" "" "PROP_schInstTempTargetLang" "Verilog"       "F" "" "" "" "PROP_sysgenInstTempTargetLang" "Verilog"       "F" "" "" "" "PROP_tbwTestbenchTargetLang" "Verilog"       "F" "" "" "" "PROP_xawHdlSourceTargetLang" "Verilog"       "F" "" "" "" "PROP_xilxPostTrceSpeed" "-1"       "F" "" "" "" "PROP_xilxPreTrceSpeed" "-1"       "F" "" "" "" "PROP_xmpInstTempTargetLang" "Verilog"       "G" "" "" "" "PROP_HdlTemplateName" "LVDS_FPGA2.v"       "G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true"       "G" "" "" "" "PROP_SimModelGenArchOnly" "false"       "G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true"       "G" "" "" "" "PROP_SimModelIncSimprimInVerilogFile" "false"       "G" "" "" "" "PROP_SimModelIncUnisimInVerilogFile" "false"       "G" "" "" "" "PROP_SimModelIncUselibDirInVerilogFile" "false"       "G" "" "" "" "PROP_SimModelNoEscapeSignal" "false"       "G" "" "" "" "PROP_SimModelOutputExtIdent" "false"       "G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure"       "G" "" "" "" "PROP_SimModelRenTopLevMod" ""       "G" "" "" "" "PROP_bencherPostMapTestbenchName" "TB_TX_RX.map_tfw"       "G" "" "" "" "PROP_bencherPostParTestbenchName" "TB_TX_RX.timesim_tfw"       "G" "" "" "" "PROP_bencherPostXlateTestbenchName" "TB_TX_RX.translate_tfw"       "G" "" "" "" "PROP_netgenPostMapSimModelName" "DDR_TX_TEST_map.v"       "G" "" "" "" "PROP_netgenPostParSimModelName" "DDR_TX_TEST_timesim.v"       "G" "" "" "" "PROP_netgenPostSynthesisSimModelName" "DDR_TX_TEST_synthesis.v"       "G" "" "" "" "PROP_netgenPostXlateSimModelName" "DDR_TX_TEST_translate.v"       "H" "" "" "" "PROP_SimModelBringOutGsrNetAsAPort" "false"       "H" "" "" "" "PROP_SimModelBringOutGtsNetAsAPort" "false"       "H" "" "" "" "PROP_SimModelPathUsedInSdfAnn" "Default"       "H" "" "" "" "PROP_netgenRenameTopLevEntTo" ""       "I" "" "" "" "PROP_SimModelGsrPortName" "GSR_PORT"       "I" "" "" "" "PROP_SimModelGtsPortName" "GTS_PORT"       "I" "" "" "" "PROP_SimModelRocPulseWidth" "100"       "I" "" "" "" "PROP_SimModelTocPulseWidth" "0"}  HandleException {    RestoreProcessProperties $iProjHelper $process_props  } "A problem occured while restoring process properties."   # library names and their members   set libraries {   }  HandleException {    RestoreSourceLibraries $iProjHelper $libraries  } "A problem occured while restoring source libraries."   # partition names for recreation   set partition_names {   }  HandleException {    RestorePartitions $partition_names  } "A problem occured while restoring partitions."   # Close the facilitator project.   CloseFacilProject $iProjHelper   # cd into the project directory before trying to open thr project   cd $project_dir   set proj_file_full_path [file join $project_dir $project_file]   INFO "Opening restored project file \"$proj_file_full_path\" ..."   # Open the restored project in the user's client application,   # which will either be the Projnav GUI or xtclsh.   project open $project_file   # Let the user know about the backed up project file.   INFO "The project \"$project_file\" was successfully recovered and opened."   if {$wasBackedUp} {      INFO ""      INFO "The original project was renamed as \"$backup_file\"."      INFO "Please open a Technical Support WebCase at"      INFO "www.xilinx.com/support/clearexpress/websupport.htm"      INFO "and submit this file, along with the project source files, for evaluation."   }}