Release 10.1.02 Map K.37 (nt)Xilinx Map Application Log File for Design 'DDR_TX_TEST'Design Information------------------Command Line   : map -ise
E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise
-intstyle ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol high -t 1 -cm area
-pr off -k 6 -lc off -power off -o DDR_TX_TEST_map.ncd DDR_TX_TEST.ngd
DDR_TX_TEST.pcf Target Device  : xc5vfx130tTarget Package : ff1738Target Speed   : -1Mapper Version : virtex5 -- $Revision: 1.46.12.2 $Mapped Date    : Tue Feb 17 17:35:06 2009Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).Running timing-driven packing...Phase 1.1Phase 1.1 (Checksum:f94b6) REAL time: 50 secs Phase 2.7INFO:Place:834 - Only a subset of IOs are locked. Out of 142 IOs, 141 are locked
   and 1 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. Phase 2.7 (Checksum:f94b6) REAL time: 54 secs Phase 3.31Phase 3.31 (Checksum:f94b6) REAL time: 54 secs Phase 4.33Phase 4.33 (Checksum:f94b6) REAL time: 59 secs Phase 5.32Phase 5.32 (Checksum:f94b6) REAL time: 59 secs Phase 6.2........Phase 6.2 (Checksum:160841) REAL time: 1 mins 23 secs Phase 7.30Phase 7.30 (Checksum:160841) REAL time: 1 mins 23 secs Phase 8.3......Phase 8.3 (Checksum:182f9e) REAL time: 1 mins 25 secs Phase 9.5Phase 9.5 (Checksum:182f9e) REAL time: 1 mins 25 secs Phase 10.8..Phase 10.8 (Checksum:710890) REAL time: 1 mins 27 secs Phase 11.29Phase 11.29 (Checksum:710890) REAL time: 1 mins 27 secs Phase 12.5Phase 12.5 (Checksum:710890) REAL time: 1 mins 27 secs Phase 13.18Phase 13.18 (Checksum:7146be) REAL time: 1 mins 35 secs Phase 14.5Phase 14.5 (Checksum:7146be) REAL time: 1 mins 35 secs Phase 15.34Phase 15.34 (Checksum:7146be) REAL time: 1 mins 35 secs REAL time consumed by placer: 1 mins 36 secs CPU  time consumed by placer: 58 secs Design Summary--------------Design Summary:Number of errors:      0Number of warnings:   69Slice Logic Utilization:  Number of Slice Registers:                   147 out of  81,920    1%    Number used as Flip Flops:                 147  Number of Slice LUTs:                        140 out of  81,920    1%    Number used as logic:                      131 out of  81,920    1%      Number using O6 output only:               3      Number using O5 output only:             119      Number using O5 and O6:                    9    Number used as exclusive route-thru:         9  Number of route-thrus:                       128 out of 163,840    1%    Number using O6 output only:               128Slice Logic Distribution:  Number of occupied Slices:                    41 out of  20,480    1%  Number of LUT Flip Flop pairs used:          150    Number with an unused Flip Flop:             3 out of     150    2%    Number with an unused LUT:                  10 out of     150    6%    Number of fully used LUT-FF pairs:         137 out of     150   91%    Number of unique control sets:               4    Number of slice register sites lost      to control set restrictions:               9 out of  81,920    1%  A LUT Flip Flop pair for this architecture represents one LUT paired with  one Flip Flop within a slice.  A control set is a unique combination of  clock, reset, set, and enable signals for a registered element.  The Slice Logic Distribution report is not meaningful if the design is  over-mapped for a non-slice resource or if Placement fails.IO Utilization:  Number of bonded IOBs:                       142 out of     840   16%    IOB Flip Flops:                             68    IOB Master Pads:                            68    IOB Slave Pads:                             68Specific Feature Utilization:  Number of BUFG/BUFGCTRLs:                      2 out of      32    6%    Number used as BUFGs:                        2  Number of PLL_ADVs:                            1 out of       6   16%Peak Memory Usage:  496 MBTotal REAL time to MAP completion:  2 mins 48 secs Total CPU time to MAP completion:   1 mins 34 secs Mapping completed.See MAP report file "DDR_TX_TEST_map.mrp" for details.