?? sysalib.s
字號:
/* Jump to usrInit. */
MOV r0, #BOOT_WARM_AUTOBOOT /* pass startType */
B _usrInit
/*******************************************************************************
*
* sysIntStackSplit - split interrupt stack and set interrupt stack pointers
*
* This routine is called, via a function pointer, during kernel
* initialisation. It splits the allocated interrupt stack into IRQ and
* SVC-mode stacks and sets the processor's IRQ stack pointer. Note that
* the pointer passed points to the bottom of the stack allocated i.e.
* highest address+1.
*
* IRQ stack needs 6 words per nested interrupt;
* SVC-mode will need a good deal more for the C interrupt handlers.
* For now, use ratio 1:7 with any excess allocated to the SVC-mode stack
* at the lowest address.
*
* Note that FIQ is not handled by VxWorks so no stack is allocated for it.
*
* The stacks and the variables that describe them look like this.
* .CS
*
* - HIGH MEMORY -
* ------------------------ <--- vxIrqIntStackBase (r0 on entry)
* | |
* | IRQ-mode |
* | interrupt stack |
* | |
* ------------------------ <--{ vxIrqIntStackEnd
* | | { vxSvcIntStackBase
* | SVC-mode |
* | interrupt stack |
* | |
* ------------------------ <--- vxSvcIntStackEnd
* - LOW MEMORY -
* .CE
*
* NOTE: This routine should not be called by the user.
* void sysIntStackSplit
* (
* char *pBotStack /@ pointer to bottom of interrupt stack @/
* long size /@ size of stack @/
* )
*/
_ARM_FUNCTION_CALLED_FROM_C(_sysIntStackSplit)
/*
* r0 = base of space allocated for stacks (i.e. highest address)
* r1 = size of space
*/
SUB r2, r0, r1 /* r2->lowest usable address */
LDR r3, L$_vxSvcIntStackEnd
STR r2, [r3] /* == end of SVC-mode stack */
SUB r2, r0, r1, ASR #3 /* leave 1/8 for IRQ */
LDR r3, L$_vxSvcIntStackBase
STR r2, [r3]
/* Allocate IRQ stack. */
LDR r3, L$_vxIrqIntStackEnd
STR r2, [r3]
LDR r3, L$_vxIrqIntStackBase
STR r0, [r3]
/* Setting irq_sp. */
MRS r2, cpsr
BIC r3, r2, #MASK_MODE
ORR r3, r3, #MODE_IRQ32 | I_BIT /* set irq_sp */
MSR cpsr, r3
MOV sp, r0
/* Switch back to original mode. */
MSR cpsr, r2
/* Return to the caller. */
MOV pc, lr
#ifndef WRITE_BUFFER_FETCHED
#define REGION_4KB ((12 - 1) << 1) /* 2^12 = 4KB */
#define REGION_8KB ((13 - 1) << 1) /* 2^13 = 8KB */
#define REGION_16KB ((14 - 1) << 1) /* 2^14 = 16KB */
#define REGION_32KB ((15 - 1) << 1) /* 2^15 = 32KB */
#define REGION_64KB ((16 - 1) << 1) /* 2^16 = 64KB */
#define REGION_128KB ((17 - 1) << 1) /* 2^17 = 128KB */
#define REGION_256KB ((18 - 1) << 1) /* 2^18 = 256KB */
#define REGION_512KB ((19 - 1) << 1) /* 2^19 = 512KB */
#define REGION_1MB ((20 - 1) << 1) /* 2^20 = 1MB */
#define REGION_2MB ((21 - 1) << 1) /* 2^21 = 2MB */
#define REGION_4MB ((22 - 1) << 1) /* 2^22 = 4MB */
#define REGION_8MB ((23 - 1) << 1) /* 2^23 = 8MB */
#define REGION_16MB ((24 - 1) << 1) /* 2^24 = 16MB */
#define REGION_32MB ((25 - 1) << 1) /* 2^25 = 32MB */
#define REGION_64MB ((26 - 1) << 1) /* 2^26 = 64MB */
#define REGION_128MB ((27 - 1) << 1) /* 2^27 = 128MB */
#define REGION_256MB ((28 - 1) << 1) /* 2^28 = 256MB */
#define REGION_512MB ((29 - 1) << 1) /* 2^29 = 512MB */
#define REGION_1GB ((30 - 1) << 1) /* 2^30 = 1GB */
#define REGION_2GB ((31 - 1) << 1) /* 2^31 = 2GB */
#define REGION_4GB ((32 - 1) << 1) /* 2^32 = 4GB */
#define REGION_ENABLE 1
#define REGION_DISABLE 0
/*******************************************************************************
*
* _sysMpuGlobalMapInit - initialize Cache and MMU
*
* void sysMpuGlobalMapInit(void)
*/
_ARM_FUNCTION_CALLED_FROM_C(_sysMpuGlobalMapInit)
/* Initialize Protection Region Register. */
LDR r1, =LOCAL_MEM_LOCAL_ADRS | REGION_32MB | REGION_ENABLE
MCR p15, 0, r1, c6, c0, 1 /* code region 0 */
MCR p15, 0, r1, c6, c0, 0 /* data region 0 */
#if (USER_RESERVED_MEM > 0)
LDR r1, =SYS_MEM_TOP | REGION_2MB | REGION_ENABLE
#else /* (USER_RESERVED_MEM > 0) */
MOV r1, #REGION_DISABLE /* disable region */
#endif /* (USER_RESERVED_MEM > 0) */
MCR p15, 0, r1, c6, c1, 1 /* code region 1 */
MCR p15, 0, r1, c6, c1, 0 /* data region 1 */
LDR r1, =ROM_BASE_ADRS | REGION_512KB | REGION_ENABLE
MCR p15, 0, r1, c6, c2, 1 /* code region 2 */
MCR p15, 0, r1, c6, c2, 0 /* data region 2 */
#ifdef INCLUDE_FLASH
LDR r1, =FLASH_BASE_ADRS | REGION_2MB | REGION_ENABLE
#else /* INCLUDE_FLASH */
MOV r1, #REGION_DISABLE /* disable region */
#endif /* INCLUDE_FLASH */
MCR p15, 0, r1, c6, c3, 1 /* code region 3 */
MCR p15, 0, r1, c6, c3, 0 /* data region 3 */
#ifdef INCLUDE_LCD
LDR r1, =LCD_BASE_ADRS | REGION_1MB | REGION_ENABLE
#else /* INCLUDE_LCD */
MOV r1, #REGION_DISABLE /* disable region */
#endif /* INCLUDE_LCD */
MCR p15, 0, r1, c6, c4, 1 /* code region 4 */
MCR p15, 0, r1, c6, c4, 0 /* data region 4 */
#ifdef INCLUDE_SRAM
LDR r1, =SRAM_BASE_ADRS | REGION_1MB | REGION_ENABLE
#else /* INCLUDE_SRAM */
MOV r1, #REGION_DISABLE /* disable region */
#endif /* INCLUDE_SRAM */
MCR p15, 0, r1, c6, c5, 1 /* code region 5 */
MCR p15, 0, r1, c6, c5, 0 /* data region 5 */
LDR r1, =S3C2510_REG_BASE_ADRS | REGION_2MB | REGION_ENABLE
MCR p15, 0, r1, c6, c6, 1 /* code region 6 */
MCR p15, 0, r1, c6, c6, 0 /* data region 6 */
MOV r1, #REGION_DISABLE /* disable region */
MCR p15, 0, r1, c6, c7, 1 /* code region 7 */
MCR p15, 0, r1, c6, c7, 0 /* data region 7 */
/* Initialize Instruction Cacheable Register. */
#ifdef USER_I_CACHE_ENABLE
MOV r1, #0x01 /* code region 0 cacheable, region 1 ~ 7 non cacheable */
#else /* USER_I_CACHE_ENABLE */
MOV r1, #0x00 /* code region 0 ~ 7 non cacheable */
#endif /* USER_I_CACHE_ENABLE */
MCR p15, 0, r1, c2, c0, 1;
/* Initialize Data Cacheable Register. */
#ifdef USER_D_CACHE_ENABLE
MOV r1, #0x01 /* data region 0 cacheable, region 1 ~ 7 non cacheable */
#else /* USER_D_CACHE_ENABLE */
MOV r1, #0x00 /* data region 0 ~ 7 non cacheable */
#endif /* USER_D_CACHE_ENABLE */
MCR p15, 0, r1, c2, c0, 0;
/* Initialize Write Buffer Control Register. */
/* We can use ARM940T WB, because ARM940T rev.2 core implemented in S3C2510A. */
MOV r1, #0xff /* data region 0 ~ 7, bufferable */
MCR p15, 0, r1, c3, c0, 0
/* Initialize Instruction Space Protection Register. */
LDR r1, =0xffff /* code region all full access */
MCR p15, 0, r1, c5, c0, 1
/* Initialize Data Space Protection Register. */
LDR r1, =0xffff /* data region all full access */
MCR p15, 0, r1, c5, c0, 0
MRC CP_MMU, 0, r1, c1, c0, 0 /* read from MMU CR */
#ifdef USER_I_CACHE_ENABLE
ORR r1, r1, #MMUCR_I_ENABLE /* Instruction cache enable */
#endif /* USER_I_CACHE_ENABLE */
#ifdef USER_D_CACHE_ENABLE
ORR r1, r1, #MMUCR_C_ENABLE /* (data) cache enable */
#endif /* USER_D_CACHE_ENABLE */
#ifdef INCLUDE_MMU
ORR r1, r1, #MMUCR_M_ENABLE /* MMU enable */
#endif /* INCLUDE_MMU */
MCR CP_MMU, 0, r1, c1, c0, 0 /* write to MMU CR */
/* Return to the caller. */
MOV pc, lr
#endif /* WRITE_BUFFER_FETCHED */
/******************************************************************************/
/*
* PC-relative-addressable pointers - LDR Rn,=sym is broken.
* note "_" after "$" to stop preprocessor preforming substitution.
*/
.balign 4
L$_vxSvcIntStackBase:
.long _vxSvcIntStackBase
L$_vxSvcIntStackEnd:
.long _vxSvcIntStackEnd
L$_vxIrqIntStackBase:
.long _vxIrqIntStackBase
L$_vxIrqIntStackEnd:
.long _vxIrqIntStackEnd
L$_sysCacheUncachedAdrs:
.long SYS_CACHE_UNCACHED_ADRS
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