//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  Header: s3c2440x_usbd.h
//
//  Defines the USB device controller CPU register layout and definitions.
//
#ifndef __S3C2440X_USBD_H
#define __S3C2440X_USBD_H

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
//
//  Type: S3C2440X_USBD_REG    
//
//  Defines the USB device control register block. This register bank is
//  located by the constant S3C2440X_BASE_REG_PA_USBD in configuration file 
//  s3c2440_base_reg_cfg.h.
//

struct FUNC_ADDR_REG   // Function Address Register
{
    UINT8 func_addr       :7;    // function_address
    UINT8 addr_up         :1;    // addr_update
};

struct PWR_REG         // Power Management Register
{
    UINT8 sus_en          :1;    // suspend_en
    UINT8 sus_mo          :1;    // suspend_mode
    UINT8 muc_res         :1;    // mcu_resume
    UINT8 usb_re          :1;    // usb_reset
    UINT8 rsvd1           :3;     
    UINT8 iso_up          :1;    // iso_update
};

struct EP_INT_REG      // Endpoint Interrupt register
{
    UINT8 ep0_int         :1;    // ep0_interrupt
    UINT8 ep1_int         :1;    // ep1_interrupt
    UINT8 ep2_int         :1;    // ep2_interrupt
    UINT8 ep3_int         :1;    // ep3_interrupt
    UINT8 ep4_int         :1;    // ep4_interrupt
    UINT8 rsvd0           :3;
};

struct USB_INT_REG     // USB Interrupt Register
{
    UINT8 sus_int         :1;    // suspend inaterrupt
    UINT8 resume_int      :1;    // resume interrupt
    UINT8 reset_int       :1;    // reset interrupt
    UINT8 rsvd0           :5;
};

struct EP_INT_EN_REG   // Endpoint Interrupt Mask Register
{
    UINT8 ep0_int_en      :1;    // ep1_int_reg
    UINT8 ep1_int_en      :1;    // ep1_int_reg
    UINT8 ep2_int_en      :1;    // ep2_int_reg
    UINT8 ep3_int_en      :1;    // ep3_int_reg
    UINT8 ep4_int_en      :1;    // ep4_int_reg
    UINT8 rsvd0           :3;
};

struct USB_INT_EN_REG  // USB Interrupt Mask Register
{
    UINT8 sus_int_en      :1;    // suspend_int_en
    UINT8 rsvd1           :1;     
    UINT8 reset_int_en    :1;    // reset_enable_reg
    UINT8 rsvd0           :5;
};

struct FRAME_NUM1_REG  // Frame Number 1 Register
{
    UINT8 fr_n1           :8;    // frame_num1_reg
};

struct FRAME_NUM2_REG  // Frame Number 2 Register
{
    UINT8 fr_n2           :8;    // frame_num2_reg
};

struct INDEX_REG       // Index Register
{
    UINT8 index           :8;    // index_reg
};

// TODO - clean this up.

struct EP0ICSR1Bits             // EP0 & ICSR1 shared
{
    UINT8 opr_ipr        :1;
    UINT8 ipr_       :1;
    UINT8 sts_ur     :1;
    UINT8 de_ff      :1;
    UINT8 se_sds     :1;
    UINT8 sds_sts        :1;
    UINT8 sopr_cdt       :1;
    UINT8 sse_       :1;
};

struct ICSR2Bits
{              // in csr2 areg
    UINT8 rsvd1      :4;
    UINT8 in_dma_int_en  :1;     // in_dma_int_en
    UINT8 mode_in        :1;     // mode_in
    UINT8 iso        :1;         // iso/bulk mode
    UINT8 auto_set       :1;     // auto_set
};

struct OCSR1Bits
{              // out csr1 reg
    UINT8 out_pkt_rdy    :1;     // out packet reday
    UINT8 rsvd1      :1;
    UINT8 ov_run     :1;     // over_run
    UINT8 data_error :1;         // data_error
    UINT8 fifo_flush :1;         // fifo_flush
    UINT8 send_stall :1;         // send_stall
    UINT8 sent_stall :1;             // sent_stall
    UINT8 clr_data_tog   :1;     // clear data toggle
};

struct OCSR2Bits
{              // out csr2 reg
    UINT8 rsvd1      :5;
    UINT8 out_dma_int_en :1;     // out_dma_int_en
    UINT8 iso        :1;     // iso/bulk mode
    UINT8 auto_clr       :1;     // auto_clr
};

struct EP0FBits
{               // ep0 fifo reg
    UINT8 fifo_data      :8;     // fifo data
};

struct EP1FBits
{               // ep0 fifo reg
    UINT8 fifo_data      :8;     // fifo data
};

struct EP2FBits
{               // ep0 fifo reg
    UINT8 fifo_data      :8;     // fifo data
};

struct EP3FBits
{               // ep0 fifo reg
    UINT8 fifo_data      :8;     // fifo data
};

struct EP4FBits
{               // ep0 fifo reg
    UINT8 fifo_data      :8;     // fifo data
};

struct MAXPBits
{
    UINT8 maxp       :4;     // max packet reg
    UINT8 rsvd0      :4;
};

struct OFCR1Bits
{              // out_fifo_cnt1_reg
    UINT8 out_cnt_low    :8;     // out_cnt_low
};

struct OFCR2Bits
{              // out_fifo_cnt2_reg
    UINT8 out_cnt_high   :8;     // out_cnt_high
};

struct EP1DCBits
{              // ep1 dma interface control
    UINT8 dma_mo_en      :1;     // dma_mode_en
    UINT8 in_dma_run     :1;     // in_dma_run
    UINT8 orb_odr        :1;     // out_run_ob/out_dma_run
    UINT8 demand_mo      :1;     // demand_mode
    UINT8 state      :3;     // state
    UINT8 in_run_ob      :1;     // in_run_ob
};

struct EP2DCBits
{              // ep2 dma interface control
    UINT8 dma_mo_en      :1;     // dma_mode_en
    UINT8 in_dma_run     :1;     // in_dma_run
    UINT8 orb_odr        :1;     // out_run_ob/out_dma_run
    UINT8 demand_mo      :1;     // demand_mode
    UINT8 state      :3;     // state
    UINT8 in_run_ob      :1;     // in_run_ob
};

struct EP3DCBits
{              // ep3 dma interface control
    UINT8 dma_mo_en      :1;     // dma_mode_en
    UINT8 in_dma_run     :1;     // in_dma_run
    UINT8 orb_odr        :1;     // out_run_ob/out_dma_run
    UINT8 demand_mo      :1;     // demand_mode
    UINT8 state      :3;     // state
    UINT8 in_run_ob      :1;     // in_run_ob
};

struct EP4DCBits
{              // ep4 dma interface control
    UINT8 dma_mo_en      :1;     // dma_mode_en
    UINT8 in_dma_run     :1;     // in_dma_run
    UINT8 orb_odr        :1;     // out_run_ob/out_dma_run
    UINT8 demand_mo      :1;     // demand_mode
    UINT8 state      :3;     // state
    UINT8 in_run_ob      :1;     // in_run_ob
};

struct EP1DUBits
{
    UINT8 ep1_unit_cnt   :8;     // ep0_unit_cnt
};

struct EP2DUBits
{
    UINT8 ep2_unit_cnt   :8;     // ep0_unit_cnt
};

struct EP3DUBits
{
    UINT8 ep3_unit_cnt   :8;     // ep0_unit_cnt
};

struct EP4DUBits
{
    UINT8 ep4_unit_cnt   :8;     // ep0_unit_cnt
};

struct EP1DFBits
{
    UINT8 ep1_fifo_cnt   :8;
};

struct EP2DFBits
{
    UINT8 ep2_fifo_cnt   :8;
};

struct EP3DFBits
{
    UINT8 ep3_fifo_cnt   :8;
};

struct EP4DFBits
{
    UINT8 ep4_fifo_cnt   :8;
};

struct EP1DTLBits
{
    UINT8 ep1_ttl_l      :8;
};

struct EP1DTMBits
{
    UINT8 ep1_ttl_m      :8;
};

struct EP1DTHBits
{
    UINT8 ep1_ttl_h      :8;
};

struct EP2DTLBits
{
    UINT8 ep2_ttl_l      :8;
};

struct EP2DTMBits
{
    UINT8 ep2_ttl_m      :8;
};

struct EP2DTHBits
{
    UINT8 ep2_ttl_h      :8;
};

struct EP3DTLBits
{
    UINT8 ep3_ttl_l      :8;
};

struct EP3DTMBits
{
    UINT8 ep3_ttl_m      :8;
};

struct EP3DTHBits
{
    UINT8 ep3_ttl_h      :8;
};

struct EP4DTLBits
{
    UINT8 ep4_ttl_l      :8;
};

struct EP4DTMBits
{
    UINT8 ep4_ttl_m      :8;
};

struct EP4DTHBits
{