//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//

// Copyright (c) 2002 BSQUARE Corporation.  All rights reserved.
// DO NOT REMOVE --- BEGIN EXTERNALLY DEVELOPED SOURCE CODE ID 40973--- DO NOT REMOVE

#ifndef __SDIOCONTROLLER_H
#define __SDIOCONTROLLER_H

//#################################### Register Constants/Masks/etc. ######################################

// NOTE: The theoretical maximum speed is 25.3 Mhz (prescaler register set to 0), but this is above the 
//       maximum allowed value of 25 MHz.  The next lower value allowed by the prescaler register on the 
//       SC2440 hardware is 12687500 Hz (prescaler register set to 1)
#define MAX_SDI_BUS_TRANSFER_SPEED		12687500				// 12.7 Mhz

#define BYTES_PER_SECTOR				512
#define SDI_CONTROLLER_FIFO_SIZE		64

//----- Register definitions for SDICON control register (global config register) -----
#define LITTLE_ENDIAN_BYTE_ORDER		0x00000000
#define SDIO_INTERRUPT_ENABLE			0x00000008 
#define SDIO_READ_WAIT_ENABLE			0x00000004 
#define SDIO_SDMCC_RESET				0x00000100
#define SDIO_CLK_TYPE_MCC				0x00000020
#define SDIO_BYTE_ORDER_B				0x00000010
#define SDIOCON_RSV1					0x00000002 
#define CLOCK_ENABLE					0x00000001				


//----- Register definitions for SDICCON control register (command config register) -----
//		NOTE:  Lowest 8 bits are used for the actual command's opcode
#define SDIO_ABORT_COMMAND				0x00001000				// Works for CMD12 and CMD52
#define SDIO_COMMAND_WITH_DATA			0x00000800
#define LONG_RESPONSE					0x00000400				
#define WAIT_FOR_RESPONSE				0x00000200				
#define START_COMMAND					0x00000100				

#define COMMAND_START_BIT				0x00000040				// Commands are 6 bits, but the 7th bit must be set!
#define MAX_CMD_VALUE					0x0000007F				// In SD/MMC clock cycles
#define	NULL_CMD_ARGUMENT				0x00000000
															
//----- Register definitions for SDICSTA control register (command status register) -----
//		NOTE:  Lowest 8 bits indicate the command's response code
#define CRC_CHECK_FAILED				0x00001000				
#define COMMAND_SENT					0x00000800
#define COMMAND_TIMED_OUT				0x00000400				
#define RESPONSE_RECEIVED				0x00000200				
#define COMMAND_IN_PROGRESS				0x00000100				

#define SHORT_RESPONSE_LENGTH			0x00000006				// In bytes
#define LONG_RESPONSE_LENGTH			0x00000010				// In bytes


//----- Register definitions for SDIDTIMER control register (data/busy config register) -----
//		NOTES:	1) Valid range		= 0-65536
//				2) Default value	= 0x2000 
#define NO_DATABUSY_TIMEOUT				0
#define MAX_DATABUSY_TIMEOUT			0x0000FFFF

//----- Register definitions for SDIDCON control register (transfer config register) -----
//		NOTE:  Lowest 12 bits are used for the block number (don't care in stream mode)
/*enable burst4 mode in DMA mode.this bit should be set only when data size is word*/
#define SDIO_BURST4_ENABLE				0x01000000
/*indicates the size of the transfer with FIFO,which is typically byte,halfword or word*/
#define SDIO_DATA_SIZE_BYTE			0x00000000
#define SDIO_DATA_SIZE_HALFW			0x00400000
#define SDIO_DATA_SIZE_WORD			0x00800000
#define SDIO_INTERRUPT_PERIOD_TYPE		0x00200000				// 0 = 2 cycles, 1 = more than 2 cycles
#define TRANSMIT_AFTER_RESPONSE			0x00100000
#define RECEIVE_AFTER_COMMAND			0x00080000
#define BUSY_AFTER_COMMAND				0x00040000
#define TRANSFER_BLOCK_MODE				0x00020000				// Clearing this bit enables stream mode
#define WIDE_BUS_ENABLE					0x00010000				
#define DMA_ENABLE						0x00008000				
#define DATA_TRANSFER_START					0x00004000
#define DATA_TRANSMIT_MODE				0x00003000
#define DATA_RECEIVE_MODE				0x00002000

// Bits 12-13 are used to determine transfer mode:
#define DATA_TRANSMIT_START				0x00003000
#define DATA_RECEIVE_START				0x00002000
#define DATA_BUSY						0x00001000
#define DATA_READY						0x00000000


//----- Register definitions for SDIDSTA control register (transfer status register) -----
#define READ_WAIT_REQUEST_OCCURED		0x00000400				
#define SDIO_INTERRUPT_DETECTED			0x00000200
#define DATA_STATS_RSV8					0x00000100
#define DATA_TRANSMIT_CRC_ERROR			0x00000080
#define DATA_RECEIVE_CRC_ERROR			0x00000040
#define DATA_TIME_OUT					0x00000020
#define DATA_TRANSMIT_FINISHED			0x00000010
#define BUSY_CHECKS_FINISH				0x00000008
#define START_BIT_ERROR					0x00000004
#define DATA_TRANSMIT_IN_PROGRESS		0x00000002
#define DATA_RECIEVE_IN_PROGRESS		0x00000001

//----- Register definitions for SDIFSTA control register (FIFO status register) -----
//		NOTE:  Lowest 7 bits indicate the number of data bytes in the FIFO
#define RESET_FIFO						0x00010000
//FIFO fail error when FIFO occurs overrun/underrun data saving. This flag is cleared by setting to one these bits.
#define FIFO_FAIL_ERROR					0x00004000	//FIFO fail
#define FIFO_FAIL_LAST_TX				0x00008000	//FIFO fail in the last transfer(only FIFO reset need)
#define FIFO_AVAIL_FOR_TX				0x00002000
#define FIFO_AVAIL_FOR_RX				0x00001000
#define TX_FIFO_HALF_FULL				0x00000800				// < 33 bytes
#define TX_FIFO_EMPTY					0x00000400				// = 0 bytes
#define RX_FIFO_LAST_DATA_READY			0x00000200
#define RX_FIFO_FULL					0x00000100				// = 64 bytes
#define RX_FIFO_HALF_FULL				0x00000080				// > 33 bytes


//----- Register definitions for SDIIMSK control register (interrupt mask register) -----
#define SDIO_NO_BUSY_INT				0x00040000
#define RESPONSE_CRC_ERROR_INT			0x00020000				
#define COMMAND_SENT_INT				0x00010000				
#define COMMAND_RESPONSE_TIMEOUT_INT	0x00008000				
#define COMMAND_RESPONSE_REC_INT		0x00004000				
#define READ_WAIT_REQUEST_INT			0x00002000				
#define SDIO_HOST_IO_INT				0x00001000				
#define FIFO_FAIL_ERROR_INT				0x00000800				
#define CRC_STATUS_ERROR_INT			0x00000400				
#define DATA_CRC_FAIL_INT				0x00000200				
#define DATA_TIMEOUT_INT				0x00000100				
#define DATA_COUNTER_ZERO_INT			0x00000080				
#define BUSY_CHECKS_COMPLETE_INT		0x00000040				
#define START_BIT_ERROR_INT				0x00000020				
#define TX_FIFO_HALF_FULL_INT			0x00000010				// < 33 bytes
#define TX_FIFO_EMPTY_INT				0x00000008				// = 0 bytes
#define RX_FIFO_LAST_DATA_READY_INT		0x00000004				
#define RX_FIFO_FULL_INT				0x00000002				// = 64 bytes
#define RX_FIFO_HALF_FULL_INT			0x00000001				// > 33 bytes

#define ERROR_INTERRUPTS_HANDLED		COMMAND_RESPONSE_TIMEOUT_INT | DATA_TIMEOUT_INT 


//###################################### Hardware Controller Structures ##################################
typedef enum {
    Idle				= -1,
    CommandSent			= 1,
    CommandComplete		= 2,
    ResponseWait		= 3,
    WriteDataTransfer	= 4,
    WriteDataTransferDone = 5,
    ProgramWait			= 6,
    WriteDataDone		= 7,
    ReadDataTransfer	= 8,
    ReadDataTransferDone = 9,
    ReadDataDone		= 10,

} SDHCDSTATE;

class CSDIOControllerBase
{
public:
    explicit CSDIOControllerBase( PSDCARD_HC_CONTEXT pHCContext );
    virtual ~CSDIOControllerBase();

    PSDCARD_HC_CONTEXT GetHostContext() const;