{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 08 20:45:35 2009 " "Info: Processing started: Thu Jan 08 20:45:35 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGA.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file VGA.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 VGA " "Info: Found entity 1: VGA" {  } { { "VGA.bdf" "" { Schematic "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGAsignal.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file VGAsignal.v" { { "Info" "ISGN_ENTITY_NAME" "1 VGAsignal " "Info: Found entity 1: VGAsignal" {  } { { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGA_Ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file VGA_Ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_Ctrl " "Info: Found entity 1: VGA_Ctrl" {  } { { "VGA_Ctrl.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA_Ctrl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "VGA " "Info: Elaborating entity \"VGA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "VGA " "Warning: Processing legacy GDF or BDF entity \"VGA\" with Max+Plus II bus and instance naming rules" {  } { { "VGA.bdf" "" { Schematic "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGAsignal VGAsignal:inst " "Info: Elaborating entity \"VGAsignal\" for hierarchy \"VGAsignal:inst\"" {  } { { "VGA.bdf" "inst" { Schematic "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 104 256 376 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 20 -1 0 } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 21 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "82 " "Info: Implemented 82 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "75 " "Info: Implemented 75 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "146 " "Info: Allocated 146 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 08 20:45:38 2009 " "Info: Processing ended: Thu Jan 08 20:45:38 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}