{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.131 ns register register " "Info: Estimated most critical path is register to register delay of 4.131 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsignal:inst\|LL\[7\] 1 REG LAB_X21_Y13 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y13; Fanout = 10; REG Node = 'VGAsignal:inst\|LL\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsignal:inst|LL[7] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.818 ns) + CELL(0.370 ns) 1.188 ns VGAsignal:inst\|LessThan10~184 2 COMB LAB_X20_Y13 2 " "Info: 2: + IC(0.818 ns) + CELL(0.370 ns) = 1.188 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'VGAsignal:inst\|LessThan10~184'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.188 ns" { VGAsignal:inst|LL[7] VGAsignal:inst|LessThan10~184 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.623 ns) 1.998 ns VGAsignal:inst\|Equal5~108 3 COMB LAB_X20_Y13 2 " "Info: 3: + IC(0.187 ns) + CELL(0.623 ns) = 1.998 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'VGAsignal:inst\|Equal5~108'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { VGAsignal:inst|LessThan10~184 VGAsignal:inst|Equal5~108 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.616 ns) 2.801 ns VGAsignal:inst\|LessThan1~137 4 COMB LAB_X20_Y13 11 " "Info: 4: + IC(0.187 ns) + CELL(0.616 ns) = 2.801 ns; Loc. = LAB_X20_Y13; Fanout = 11; COMB Node = 'VGAsignal:inst\|LessThan1~137'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { VGAsignal:inst|Equal5~108 VGAsignal:inst|LessThan1~137 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.660 ns) 4.131 ns VGAsignal:inst\|LL\[2\] 5 REG LAB_X21_Y13 7 " "Info: 5: + IC(0.670 ns) + CELL(0.660 ns) = 4.131 ns; Loc. = LAB_X21_Y13; Fanout = 7; REG Node = 'VGAsignal:inst\|LL\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.330 ns" { VGAsignal:inst|LessThan1~137 VGAsignal:inst|LL[2] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.269 ns ( 54.93 % ) " "Info: Total cell delay = 2.269 ns ( 54.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.862 ns ( 45.07 % ) " "Info: Total interconnect delay = 1.862 ns ( 45.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.131 ns" { VGAsignal:inst|LL[7] VGAsignal:inst|LessThan10~184 VGAsignal:inst|Equal5~108 VGAsignal:inst|LessThan1~137 VGAsignal:inst|LL[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X14_Y0 X28_Y14 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_HS 0 " "Info: Pin \"VGA_HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_VS 0 " "Info: Pin \"VGA_VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R 0 " "Info: Pin \"VGA_R\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G 0 " "Info: Pin \"VGA_G\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B 0 " "Info: Pin \"VGA_B\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.fit.smsg " "Info: Generated suppressed messages file D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 08 20:45:42 2009 " "Info: Processing ended: Thu Jan 08 20:45:42 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}