?? vga.tan.qmsg
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "reset register register VGAsignal:inst\|MMD\[0\] VGAsignal:inst\|MMD\[1\] 360.1 MHz Internal " "Info: Clock \"reset\" Internal fmax is restricted to 360.1 MHz between source register \"VGAsignal:inst\|MMD\[0\]\" and destination register \"VGAsignal:inst\|MMD\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.761 ns + Longest register register " "Info: + Longest register to register delay is 0.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsignal:inst\|MMD\[0\] 1 REG LCFF_X21_Y13_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y13_N1; Fanout = 5; REG Node = 'VGAsignal:inst\|MMD\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsignal:inst|MMD[0] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.447 ns) + CELL(0.206 ns) 0.653 ns VGAsignal:inst\|MMD~36 2 COMB LCCOMB_X21_Y13_N2 1 " "Info: 2: + IC(0.447 ns) + CELL(0.206 ns) = 0.653 ns; Loc. = LCCOMB_X21_Y13_N2; Fanout = 1; COMB Node = 'VGAsignal:inst\|MMD~36'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { VGAsignal:inst|MMD[0] VGAsignal:inst|MMD~36 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.761 ns VGAsignal:inst\|MMD\[1\] 3 REG LCFF_X21_Y13_N3 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.761 ns; Loc. = LCFF_X21_Y13_N3; Fanout = 3; REG Node = 'VGAsignal:inst\|MMD\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { VGAsignal:inst|MMD~36 VGAsignal:inst|MMD[1] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 41.26 % ) " "Info: Total cell delay = 0.314 ns ( 41.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.447 ns ( 58.74 % ) " "Info: Total interconnect delay = 0.447 ns ( 58.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.761 ns" { VGAsignal:inst|MMD[0] VGAsignal:inst|MMD~36 VGAsignal:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.761 ns" { VGAsignal:inst|MMD[0] {} VGAsignal:inst|MMD~36 {} VGAsignal:inst|MMD[1] {} } { 0.000ns 0.447ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset destination 4.285 ns + Shortest register " "Info: + Shortest clock path from clock \"reset\" to destination register is 4.285 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 CLK PIN_56 29 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 29; CLK Node = 'reset'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 144 24 192 160 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.635 ns) + CELL(0.666 ns) 4.285 ns VGAsignal:inst\|MMD\[1\] 2 REG LCFF_X21_Y13_N3 3 " "Info: 2: + IC(2.635 ns) + CELL(0.666 ns) = 4.285 ns; Loc. = LCFF_X21_Y13_N3; Fanout = 3; REG Node = 'VGAsignal:inst\|MMD\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.301 ns" { reset VGAsignal:inst|MMD[1] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 38.51 % ) " "Info: Total cell delay = 1.650 ns ( 38.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.635 ns ( 61.49 % ) " "Info: Total interconnect delay = 2.635 ns ( 61.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.285 ns" { reset VGAsignal:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.285 ns" { reset {} reset~combout {} VGAsignal:inst|MMD[1] {} } { 0.000ns 0.000ns 2.635ns } { 0.000ns 0.984ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset source 4.285 ns - Longest register " "Info: - Longest clock path from clock \"reset\" to source register is 4.285 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 CLK PIN_56 29 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 29; CLK Node = 'reset'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 144 24 192 160 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.635 ns) + CELL(0.666 ns) 4.285 ns VGAsignal:inst\|MMD\[0\] 2 REG LCFF_X21_Y13_N1 5 " "Info: 2: + IC(2.635 ns) + CELL(0.666 ns) = 4.285 ns; Loc. = LCFF_X21_Y13_N1; Fanout = 5; REG Node = 'VGAsignal:inst\|MMD\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.301 ns" { reset VGAsignal:inst|MMD[0] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 38.51 % ) " "Info: Total cell delay = 1.650 ns ( 38.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.635 ns ( 61.49 % ) " "Info: Total interconnect delay = 2.635 ns ( 61.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.285 ns" { reset VGAsignal:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.285 ns" { reset {} reset~combout {} VGAsignal:inst|MMD[0] {} } { 0.000ns 0.000ns 2.635ns } { 0.000ns 0.984ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.285 ns" { reset VGAsignal:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.285 ns" { reset {} reset~combout {} VGAsignal:inst|MMD[1] {} } { 0.000ns 0.000ns 2.635ns } { 0.000ns 0.984ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.285 ns" { reset VGAsignal:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.285 ns" { reset {} reset~combout {} VGAsignal:inst|MMD[0] {} } { 0.000ns 0.000ns 2.635ns } { 0.000ns 0.984ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 38 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 38 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.761 ns" { VGAsignal:inst|MMD[0] VGAsignal:inst|MMD~36 VGAsignal:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.761 ns" { VGAsignal:inst|MMD[0] {} VGAsignal:inst|MMD~36 {} VGAsignal:inst|MMD[1] {} } { 0.000ns 0.447ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.285 ns" { reset VGAsignal:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.285 ns" { reset {} reset~combout {} VGAsignal:inst|MMD[1] {} } { 0.000ns 0.000ns 2.635ns } { 0.000ns 0.984ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.285 ns" { reset VGAsignal:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.285 ns" { reset {} reset~combout {} VGAsignal:inst|MMD[0] {} } { 0.000ns 0.000ns 2.635ns } { 0.000ns 0.984ns 0.666ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsignal:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { VGAsignal:inst|MMD[1] {} } { } { } "" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 38 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk VGA_B VGAsignal:inst\|LL\[4\] 21.715 ns register " "Info: tco from clock \"clk\" to destination pin \"VGA_B\" through register \"VGAsignal:inst\|LL\[4\]\" is 21.715 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.462 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 128 24 192 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns VGAsignal:inst\|clk_25 2 REG LCFF_X1_Y6_N3 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y6_N3; Fanout = 3; REG Node = 'VGAsignal:inst\|clk_25'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk VGAsignal:inst|clk_25 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.154 ns) + CELL(0.970 ns) 5.756 ns VGAsignal:inst\|VGA_HS 3 REG LCFF_X25_Y7_N31 4 " "Info: 3: + IC(2.154 ns) + CELL(0.970 ns) = 5.756 ns; Loc. = LCFF_X25_Y7_N31; Fanout = 4; REG Node = 'VGAsignal:inst\|VGA_HS'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.124 ns" { VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.000 ns) 6.935 ns VGAsignal:inst\|VGA_HS~clkctrl 4 COMB CLKCTRL_G6 12 " "Info: 4: + IC(1.179 ns) + CELL(0.000 ns) = 6.935 ns; Loc. = CLKCTRL_G6; Fanout = 12; COMB Node = 'VGAsignal:inst\|VGA_HS~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.179 ns" { VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.666 ns) 8.462 ns VGAsignal:inst\|LL\[4\] 5 REG LCFF_X21_Y13_N19 9 " "Info: 5: + IC(0.861 ns) + CELL(0.666 ns) = 8.462 ns; Loc. = LCFF_X21_Y13_N19; Fanout = 9; REG Node = 'VGAsignal:inst\|LL\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[4] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 44.27 % ) " "Info: Total cell delay = 3.746 ns ( 44.27 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.716 ns ( 55.73 % ) " "Info: Total interconnect delay = 4.716 ns ( 55.73 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.462 ns" { clk VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.462 ns" { clk {} clk~combout {} VGAsignal:inst|clk_25 {} VGAsignal:inst|VGA_HS {} VGAsignal:inst|VGA_HS~clkctrl {} VGAsignal:inst|LL[4] {} } { 0.000ns 0.000ns 0.522ns 2.154ns 1.179ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.949 ns + Longest register pin " "Info: + Longest register to pin delay is 12.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsignal:inst\|LL\[4\] 1 REG LCFF_X21_Y13_N19 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y13_N19; Fanout = 9; REG Node = 'VGAsignal:inst\|LL\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsignal:inst|LL[4] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.258 ns) + CELL(0.370 ns) 2.628 ns VGAsignal:inst\|LessThan11~141 2 COMB LCCOMB_X20_Y13_N8 2 " "Info: 2: + IC(2.258 ns) + CELL(0.370 ns) = 2.628 ns; Loc. = LCCOMB_X20_Y13_N8; Fanout = 2; COMB Node = 'VGAsignal:inst\|LessThan11~141'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { VGAsignal:inst|LL[4] VGAsignal:inst|LessThan11~141 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.123 ns) + CELL(0.651 ns) 4.402 ns VGAsignal:inst\|LessThan9~194 3 COMB LCCOMB_X20_Y10_N24 2 " "Info: 3: + IC(1.123 ns) + CELL(0.651 ns) = 4.402 ns; Loc. = LCCOMB_X20_Y10_N24; Fanout = 2; COMB Node = 'VGAsignal:inst\|LessThan9~194'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.774 ns" { VGAsignal:inst|LessThan11~141 VGAsignal:inst|LessThan9~194 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 115 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.118 ns) + CELL(0.624 ns) 6.144 ns VGAsignal:inst\|B~1407 4 COMB LCCOMB_X21_Y7_N8 1 " "Info: 4: + IC(1.118 ns) + CELL(0.624 ns) = 6.144 ns; Loc. = LCCOMB_X21_Y7_N8; Fanout = 1; COMB Node = 'VGAsignal:inst\|B~1407'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.742 ns" { VGAsignal:inst|LessThan9~194 VGAsignal:inst|B~1407 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.092 ns) + CELL(0.370 ns) 7.606 ns VGAsignal:inst\|B~1411 5 COMB LCCOMB_X20_Y10_N20 1 " "Info: 5: + IC(1.092 ns) + CELL(0.370 ns) = 7.606 ns; Loc. = LCCOMB_X20_Y10_N20; Fanout = 1; COMB Node = 'VGAsignal:inst\|B~1411'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { VGAsignal:inst|B~1407 VGAsignal:inst|B~1411 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.237 ns) + CELL(3.106 ns) 12.949 ns VGA_B 6 PIN PIN_114 0 " "Info: 6: + IC(2.237 ns) + CELL(3.106 ns) = 12.949 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'VGA_B'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.343 ns" { VGAsignal:inst|B~1411 VGA_B } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 192 448 624 208 "VGA_B" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.121 ns ( 39.55 % ) " "Info: Total cell delay = 5.121 ns ( 39.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.828 ns ( 60.45 % ) " "Info: Total interconnect delay = 7.828 ns ( 60.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.949 ns" { VGAsignal:inst|LL[4] VGAsignal:inst|LessThan11~141 VGAsignal:inst|LessThan9~194 VGAsignal:inst|B~1407 VGAsignal:inst|B~1411 VGA_B } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.949 ns" { VGAsignal:inst|LL[4] {} VGAsignal:inst|LessThan11~141 {} VGAsignal:inst|LessThan9~194 {} VGAsignal:inst|B~1407 {} VGAsignal:inst|B~1411 {} VGA_B {} } { 0.000ns 2.258ns 1.123ns 1.118ns 1.092ns 2.237ns } { 0.000ns 0.370ns 0.651ns 0.624ns 0.370ns 3.106ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.462 ns" { clk VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.462 ns" { clk {} clk~combout {} VGAsignal:inst|clk_25 {} VGAsignal:inst|VGA_HS {} VGAsignal:inst|VGA_HS~clkctrl {} VGAsignal:inst|LL[4] {} } { 0.000ns 0.000ns 0.522ns 2.154ns 1.179ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.949 ns" { VGAsignal:inst|LL[4] VGAsignal:inst|LessThan11~141 VGAsignal:inst|LessThan9~194 VGAsignal:inst|B~1407 VGAsignal:inst|B~1411 VGA_B } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.949 ns" { VGAsignal:inst|LL[4] {} VGAsignal:inst|LessThan11~141 {} VGAsignal:inst|LessThan9~194 {} VGAsignal:inst|B~1407 {} VGAsignal:inst|B~1411 {} VGA_B {} } { 0.000ns 2.258ns 1.123ns 1.118ns 1.092ns 2.237ns } { 0.000ns 0.370ns 0.651ns 0.624ns 0.370ns 3.106ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset VGA_B 16.048 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"VGA_B\" is 16.048 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 CLK PIN_56 29 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 29; CLK Node = 'reset'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 144 24 192 160 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.783 ns) + CELL(0.650 ns) 9.417 ns VGAsignal:inst\|B~1412 2 COMB LCCOMB_X21_Y13_N4 1 " "Info: 2: + IC(7.783 ns) + CELL(0.650 ns) = 9.417 ns; Loc. = LCCOMB_X21_Y13_N4; Fanout = 1; COMB Node = 'VGAsignal:inst\|B~1412'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.433 ns" { reset VGAsignal:inst|B~1412 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.082 ns) + CELL(0.206 ns) 10.705 ns VGAsignal:inst\|B~1411 3 COMB LCCOMB_X20_Y10_N20 1 " "Info: 3: + IC(1.082 ns) + CELL(0.206 ns) = 10.705 ns; Loc. = LCCOMB_X20_Y10_N20; Fanout = 1; COMB Node = 'VGAsignal:inst\|B~1411'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { VGAsignal:inst|B~1412 VGAsignal:inst|B~1411 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.237 ns) + CELL(3.106 ns) 16.048 ns VGA_B 4 PIN PIN_114 0 " "Info: 4: + IC(2.237 ns) + CELL(3.106 ns) = 16.048 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'VGA_B'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.343 ns" { VGAsignal:inst|B~1411 VGA_B } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "D:/FPGA開發板/開發板資料/EP2C5_EP2C8-V5資料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 192 448 624 208 "VGA_B" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.946 ns ( 30.82 % ) " "Info: Total cell delay = 4.946 ns ( 30.82 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.102 ns ( 69.18 % ) " "Info: Total interconnect delay = 11.102 ns ( 69.18 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.048 ns" { reset VGAsignal:inst|B~1412 VGAsignal:inst|B~1411 VGA_B } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.048 ns" { reset {} reset~combout {} VGAsignal:inst|B~1412 {} VGAsignal:inst|B~1411 {} VGA_B {} } { 0.000ns 0.000ns 7.783ns 1.082ns 2.237ns } { 0.000ns 0.984ns 0.650ns 0.206ns 3.106ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
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