`timescale 1ns/1psmodule ram_top;reg clk,rst;wire [3:0] q;always #10 clk=~clk;initial 	begin		clk=0;rst=1;		#50 rst<=0;		#50 rst<=1;	end										ram_control ram_control(.clk(clk),.rst(rst),.q(q));endmodule