EDA Netlist Writer report for ram_control
Sat Jul 29 11:10:31 2006
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Tool Settings
  4. Simulation Tool Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sat Jul 29 11:10:31 2006 ;
; Revision Name             ; ram_control                           ;
; Top-level Entity Name     ; ram_control                           ;
; Family                    ; Cyclone                               ;
; Simulation Tool Writer    ; Successful                            ;
+---------------------------+---------------------------------------+


+---------------------------------------------------------------------------+
; Simulation Tool Settings                                                  ;
+------------------------------------------------------+--------------------+
; Option                                               ; Setting            ;
+------------------------------------------------------+--------------------+
; Tool Name                                            ; ModelSim (Verilog) ;
; Generate Netlist for Functional Simulation Only      ; Off                ;
; Time scale                                           ; 1 ps               ;
; Truncate long hierarchy paths                        ; Off                ;
; Map illegal HDL characters                           ; Off                ;
; Flatten buses into individual nodes                  ; Off                ;
; Maintain hierarchy                                   ; Off                ;
; Bring out device-wide set/reset signals as ports     ; Off                ;
; Output Excalibur stripe as a single module or entity ; Off                ;
; Enable glitch filtering                              ; Off                ;
+------------------------------------------------------+--------------------+


+--------------------------------------------------------------------------------------------+
; Simulation Tool Generated Files                                                            ;
+--------------------------------------------------------------------------------------------+
; Generated Files                                                                            ;
+--------------------------------------------------------------------------------------------+
; E:/farsight_fpga_course/code/high/onchip ram/quartus/simulation/modelsim/ram_control.vo    ;
; E:/farsight_fpga_course/code/high/onchip ram/quartus/simulation/modelsim/ram_control_v.sdo ;
+--------------------------------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Sat Jul 29 11:10:29 2006
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ram_control -c ram_control
Info: Generated files "ram_control.vo" and "ram_control_v.sdo" in directory "E:/farsight_fpga_course/code/high/onchip ram/quartus/simulation/modelsim/" for EDA simulation tool
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Jul 29 11:10:31 2006
    Info: Elapsed time: 00:00:02