?? ram_control.fit.rpt
字號:
Fitter report for ram_control
Sat Jul 29 11:10:21 2006
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Pin-Out File
7. Fitter Resource Usage Summary
8. Input Pins
9. Output Pins
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. Fitter Resource Utilization by Entity
14. Delay Chain Summary
15. Pad To Core Delay Chain Fanout
16. Control Signals
17. Global & Other Fast Signals
18. Non-Global High Fan-Out Signals
19. Fitter RAM Summary
20. Interconnect Usage Summary
21. LAB Logic Elements
22. LAB-wide Signals
23. LAB Signals Sourced
24. LAB Signals Sourced Out
25. LAB Distinct Inputs
26. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
; Fitter Status ; Successful - Sat Jul 29 11:10:21 2006 ;
; Quartus II Version ; 5.0 Build 171 11/03/2005 SP 2 SJ Full Version ;
; Revision Name ; ram_control ;
; Top-level Entity Name ; ram_control ;
; Family ; Cyclone ;
; Device ; EP1C6Q240C8 ;
; Timing Models ; Final ;
; Total logic elements ; 21 / 5,980 ( < 1 % ) ;
; Total pins ; 6 / 185 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 64 / 92,160 ( < 1 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-----------------------+-----------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP1C6Q240C8 ; ;
; Use smart compilation ; Off ; Off ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Cyclone ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
; Perform Register Duplication ; Off ; Off ;
; Perform Register Retiming ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Off ; Off ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
+----------------------------------------------------+--------------------------------+--------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Active Serial ;
; Error detection CRC ; Off ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.fit.eqn.
+--------------+
; Pin-Out File ;
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