library verilog;use verilog.vl_types.all;entity altmult_add is    generic(        width_a         : integer := 1;        width_b         : integer := 1;        width_result    : integer := 3;        number_of_multipliers: integer := 1;        lpm_type        : string  := "altmult_add";        lpm_hint        : string  := "UNUSED";        multiplier1_direction: string  := "UNUSED";        multiplier3_direction: string  := "UNUSED";        input_register_a0: string  := "CLOCK0";        input_aclr_a0   : string  := "ACLR3";        input_source_a0 : string  := "DATAA";        input_register_a1: string  := "CLOCK0";        input_aclr_a1   : string  := "ACLR3";        input_source_a1 : string  := "DATAA";        input_register_a2: string  := "CLOCK0";        input_aclr_a2   : string  := "ACLR3";        input_source_a2 : string  := "DATAA";        input_register_a3: string  := "CLOCK0";        input_aclr_a3   : string  := "ACLR3";        input_source_a3 : string  := "DATAA";        port_signa      : string  := "PORT_CONNECTIVITY";        representation_a: string  := "UNUSED";        signed_register_a: string  := "CLOCK0";        signed_aclr_a   : string  := "ACLR3";        signed_pipeline_register_a: string  := "CLOCK0";        signed_pipeline_aclr_a: string  := "ACLR3";        input_register_b0: string  := "CLOCK0";        input_aclr_b0   : string  := "ACLR3";        input_source_b0 : string  := "DATAB";        input_register_b1: string  := "CLOCK0";        input_aclr_b1   : string  := "ACLR3";        input_source_b1 : string  := "DATAB";        input_register_b2: string  := "CLOCK0";        input_aclr_b2   : string  := "ACLR3";        input_source_b2 : string  := "DATAB";        input_register_b3: string  := "CLOCK0";        input_aclr_b3   : string  := "ACLR3";        input_source_b3 : string  := "DATAB";        port_signb      : string  := "PORT_CONNECTIVITY";        representation_b: string  := "UNUSED";        signed_register_b: string  := "CLOCK0";        signed_aclr_b   : string  := "ACLR3";        signed_pipeline_register_b: string  := "CLOCK0";        signed_pipeline_aclr_b: string  := "ACLR3";        multiplier_register0: string  := "CLOCK0";        multiplier_aclr0: string  := "ACLR3";        multiplier_register1: string  := "CLOCK0";        multiplier_aclr1: string  := "ACLR3";        multiplier_register2: string  := "CLOCK0";        multiplier_aclr2: string  := "ACLR3";        multiplier_register3: string  := "CLOCK0";        multiplier_aclr3: string  := "ACLR3";        port_addnsub1   : string  := "PORT_CONNECTIVITY";        addnsub_multiplier_register1: string  := "CLOCK0";        addnsub_multiplier_aclr1: string  := "ACLR3";        addnsub_multiplier_pipeline_register1: string  := "CLOCK0";        addnsub_multiplier_pipeline_aclr1: string  := "ACLR3";        port_addnsub3   : string  := "PORT_CONNECTIVITY";        addnsub_multiplier_register3: string  := "CLOCK0";        addnsub_multiplier_aclr3: string  := "ACLR3";        addnsub_multiplier_pipeline_register3: string  := "CLOCK0";        addnsub_multiplier_pipeline_aclr3: string  := "ACLR3";        addnsub1_round_aclr: string  := "ACLR3";        addnsub1_round_pipeline_aclr: string  := "ACLR3";        addnsub1_round_register: string  := "CLOCK0";        addnsub1_round_pipeline_register: string  := "CLOCK0";        addnsub3_round_aclr: string  := "ACLR3";        addnsub3_round_pipeline_aclr: string  := "ACLR3";        addnsub3_round_register: string  := "CLOCK0";        addnsub3_round_pipeline_register: string  := "CLOCK0";        mult01_round_aclr: string  := "ACLR3";        mult01_round_register: string  := "CLOCK0";        mult01_saturation_register: string  := "CLOCK0";        mult01_saturation_aclr: string  := "ACLR3";        mult23_round_register: string  := "CLOCK0";        mult23_round_aclr: string  := "ACLR3";        mult23_saturation_register: string  := "CLOCK0";        mult23_saturation_aclr: string  := "ACLR3";        multiplier01_rounding: string  := "NO";        multiplier01_saturation: string  := "NO";        multiplier23_rounding: string  := "NO";        multiplier23_saturation: string  := "NO";        adder1_rounding : string  := "NO";        adder3_rounding : string  := "NO";        port_mult0_is_saturated: string  := "UNUSED";        port_mult1_is_saturated: string  := "UNUSED";        port_mult2_is_saturated: string  := "UNUSED";        port_mult3_is_saturated: string  := "UNUSED";        output_register : string  := "CLOCK0";        output_aclr     : string  := "ACLR0";        extra_latency   : integer := 0;        dedicated_multiplier_circuitry: string  := "AUTO";        dsp_block_balancing: string  := "AUTO";        intended_device_family: string  := "Stratix"    );    port(        dataa           : in     vl_logic_vector;        datab           : in     vl_logic_vector;        scanina         : in     vl_logic_vector;        scaninb         : in     vl_logic_vector;        sourcea         : in     vl_logic_vector;        sourceb         : in     vl_logic_vector;        clock3          : in     vl_logic;        clock2          : in     vl_logic;        clock1          : in     vl_logic;        clock0          : in     vl_logic;        aclr3           : in     vl_logic;        aclr2           : in     vl_logic;        aclr1           : in     vl_logic;        aclr0           : in     vl_logic;        ena3            : in     vl_logic;        ena2            : in     vl_logic;        ena1            : in     vl_logic;        ena0            : in     vl_logic;        signa           : in     vl_logic;        signb           : in     vl_logic;        addnsub1        : in     vl_logic;        addnsub3        : in     vl_logic;        result          : out    vl_logic_vector;        scanouta        : out    vl_logic_vector;        scanoutb        : out    vl_logic_vector;        mult01_round    : in     vl_logic;        mult23_round    : in     vl_logic;        mult01_saturation: in     vl_logic;        mult23_saturation: in     vl_logic;        addnsub1_round  : in     vl_logic;        addnsub3_round  : in     vl_logic;        mult0_is_saturated: out    vl_logic;        mult1_is_saturated: out    vl_logic;        mult2_is_saturated: out    vl_logic;        mult3_is_saturated: out    vl_logic    );end altmult_add;