?? bin27seg.tan.rpt
字號:
Classic Timing Analyzer report for bin27seg
Sun Feb 18 12:43:25 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 9.868 ns ; data_in[3] ; data_out[4] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F780C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------------+-------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------------+-------------+
; N/A ; None ; 9.868 ns ; data_in[3] ; data_out[4] ;
; N/A ; None ; 9.852 ns ; data_in[3] ; data_out[0] ;
; N/A ; None ; 9.750 ns ; data_in[3] ; data_out[5] ;
; N/A ; None ; 9.747 ns ; data_in[3] ; data_out[2] ;
; N/A ; None ; 9.720 ns ; data_in[1] ; data_out[4] ;
; N/A ; None ; 9.699 ns ; data_in[1] ; data_out[0] ;
; N/A ; None ; 9.614 ns ; data_in[2] ; data_out[4] ;
; N/A ; None ; 9.602 ns ; data_in[1] ; data_out[5] ;
; N/A ; None ; 9.593 ns ; data_in[2] ; data_out[0] ;
; N/A ; None ; 9.592 ns ; data_in[1] ; data_out[2] ;
; N/A ; None ; 9.496 ns ; data_in[2] ; data_out[5] ;
; N/A ; None ; 9.485 ns ; data_in[2] ; data_out[2] ;
; N/A ; None ; 9.433 ns ; data_in[0] ; data_out[4] ;
; N/A ; None ; 9.416 ns ; data_in[3] ; data_out[3] ;
; N/A ; None ; 9.409 ns ; data_in[0] ; data_out[0] ;
; N/A ; None ; 9.312 ns ; data_in[0] ; data_out[5] ;
; N/A ; None ; 9.310 ns ; data_in[0] ; data_out[2] ;
; N/A ; None ; 9.291 ns ; data_in[3] ; data_out[1] ;
; N/A ; None ; 9.268 ns ; data_in[1] ; data_out[3] ;
; N/A ; None ; 9.158 ns ; data_in[2] ; data_out[3] ;
; N/A ; None ; 9.137 ns ; data_in[1] ; data_out[1] ;
; N/A ; None ; 9.118 ns ; data_in[3] ; data_out[6] ;
; N/A ; None ; 9.027 ns ; data_in[2] ; data_out[1] ;
; N/A ; None ; 8.975 ns ; data_in[0] ; data_out[3] ;
; N/A ; None ; 8.960 ns ; data_in[1] ; data_out[6] ;
; N/A ; None ; 8.857 ns ; data_in[0] ; data_out[1] ;
; N/A ; None ; 8.849 ns ; data_in[2] ; data_out[6] ;
; N/A ; None ; 8.848 ns ; EN ; data_out[6] ;
; N/A ; None ; 8.848 ns ; EN ; data_out[1] ;
; N/A ; None ; 8.846 ns ; EN ; data_out[3] ;
; N/A ; None ; 8.834 ns ; EN ; data_out[2] ;
; N/A ; None ; 8.833 ns ; EN ; data_out[5] ;
; N/A ; None ; 8.833 ns ; EN ; data_out[4] ;
; N/A ; None ; 8.831 ns ; EN ; data_out[0] ;
; N/A ; None ; 8.681 ns ; data_in[0] ; data_out[6] ;
+-------+-------------------+-----------------+------------+-------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Sun Feb 18 12:43:24 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bin27seg -c bin27seg --timing_analysis_only
Info: Longest tpd from source pin "data_in[3]" to destination pin "data_out[4]" is 9.868 ns
Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G27; Fanout = 7; PIN Node = 'data_in[3]'
Info: 2: + IC(3.961 ns) + CELL(0.183 ns) = 5.378 ns; Loc. = LC_X17_Y30_N9; Fanout = 1; COMB Node = 'Mux2~10'
Info: 3: + IC(0.776 ns) + CELL(0.183 ns) = 6.337 ns; Loc. = LC_X19_Y30_N2; Fanout = 1; COMB Node = 'data_out~32'
Info: 4: + IC(1.127 ns) + CELL(2.404 ns) = 9.868 ns; Loc. = PIN_K19; Fanout = 0; PIN Node = 'data_out[4]'
Info: Total cell delay = 4.004 ns ( 40.58 % )
Info: Total interconnect delay = 5.864 ns ( 59.42 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 102 megabytes of memory during processing
Info: Processing ended: Sun Feb 18 12:43:25 2007
Info: Elapsed time: 00:00:01
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