-- 4.2.1  VHDL基本組成

-------------------------------------------------------------------------------
-- DESCRIPTION   :   BIN to seven segments converter segment encoding
--                        a
--                      +---+ 
--                    f |   | b
--                      +---+  <- g
--                    e |   | c
--                      +---+
--                        d
--                  Enable (EN) active                : high
--                  Outputs (data_out) active         : low
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity bin27seg is
	port (
		data_in : in std_logic_vector (3 downto 0);
		EN : in std_logic;
		data_out : out std_logic_vector (6 downto 0)
	);
end entity;

architecture bin27seg_arch of bin27seg is
begin

	process(data_in, EN)
	begin
		data_out <= (others => '1');
		if EN='1' then
			case data_in is
				when "0000" => data_out <= "1000000"; -- 0
				when "0001" => data_out <= "1111001"; -- 1
				when "0010" => data_out <= "0100100"; -- 2
				when "0011" => data_out <= "0110000"; -- 3
				when "0100" => data_out <= "0011001"; -- 4
				when "0101" => data_out <= "0010010"; -- 5
				when "0110" => data_out <= "0000011"; -- 6
				when "0111" => data_out <= "1111000"; -- 7
				when "1000" => data_out <= "0000000"; -- 8
				when "1001" => data_out <= "0011000"; -- 9
				when "1010" => data_out <= "0001000"; -- A
				when "1011" => data_out <= "0000011"; -- b
				when "1100" => data_out <= "0100111"; -- c
				when "1101" => data_out <= "0100001"; -- d
				when "1110" => data_out <= "0000110"; -- E
				when "1111" => data_out <= "0001110"; -- F
				when others => NULL;
			end case;
		end if;
	end process;

end bin27seg_arch;