FILES
{
	BDF_FILE = rd_contr.bdf;
	BDF_FILE = contrIQ.bdf;
	VHDL_FILE = oesel.vhd;
	BDF_FILE = indatamux.bdf;
	VHDL_FILE = rh_lpm_dff0.vhd;
	VHDL_FILE = subdiv2.vhd;
	VHDL_FILE = adddiv2.vhd;
	VHDL_FILE = rh_lpm_add_sub1.vhd;
	VHDL_FILE = rd_contract.vhd;
	VHDL_FILE = rh_lpm_mult0.vhd;
	VHDL_FILE = expand.vhd;
	VHDL_FILE = sw1_4.vhd;
	BDF_FILE = rader_hilbert.bdf;
	VECTOR_TEXT_FILE = rader_hilbert.vec;
	VECTOR_WAVEFORM_FILE = ad_end8.vwf;
}
COMPILER_SETTINGS_LIST
{
	COMPILER_SETTINGS = rader_hilbert;
	COMPILER_SETTINGS = sw1_4;
	COMPILER_SETTINGS = oesel;
	COMPILER_SETTINGS = contract;
	COMPILER_SETTINGS = ad_end_defact;
}
SIMULATOR_SETTINGS_LIST
{
	SIMULATOR_SETTINGS = oesel;
	SIMULATOR_SETTINGS = sw1_4;
	SIMULATOR_SETTINGS = rader_hilbert;
	SIMULATOR_SETTINGS = ad_end_defact;
}
SOFTWARE_SETTINGS_LIST
{
	SOFTWARE_SETTINGS = Debug;
	SOFTWARE_SETTINGS = Release;
}