?? hdli.vhd
字號:
return RESULT;
end;
function "+" (A: std_logic; B: std_logic_vector)
return std_logic_Vector is
variable RESULT: std_logic_Vector(B'length-1 downto 0);
begin
result := B;
if not (A='1' or A='H') then return result; end if;
for I in RESULT'reverse_range loop
result(i) := not B(i);
exit when result(i)='1';
end loop;
return RESULT;
end;
------------------------------------------------------------------------
function "-" (A, B: Std_Logic_Vector) return Std_Logic_Vector is
constant LEN : integer := max(A'length,B'length);
variable RESULT,left,right : Std_Logic_Vector( LEN-1 downto 0);
variable carry: std_logic;
variable lt, rt: std_logic;
begin
left := HDLi_ZeroExtend(A,result'length);
right := not(HDLi_ZeroExtend(B,result'length));
carry := '1';
for I in RESULT'reverse_range loop
lt := left(I);
rt := right(I);
RESULT(I) := lt xor rt xor carry;
carry := (lt and rt) or (lt and carry) or (rt and carry);
end loop;
return RESULT;
end;
function "-" (A: std_logic_Vector; B: std_logic)
return std_logic_Vector is
variable RESULT: std_logic_Vector(A'length-1 downto 0);
begin
result := A;
if not (B='1' or B='H') then return result; end if;
for I in RESULT'reverse_range loop
result(i) := not A(i);
exit when result(i)='0';
end loop;
return RESULT;
end;
function "-" (A: std_logic; B: std_logic_vector)
return std_logic_Vector is
variable RESULT: std_logic_Vector(B'length-1 downto 0);
begin
result := B;
if not (A='1' or A='H') then return result; end if;
for I in RESULT'reverse_range loop
result(i) := not B(i);
exit when result(i)='0';
end loop;
return RESULT;
end;
function "-"(A: std_logic_Vector) return std_logic_Vector is
variable RESULT : std_logic_Vector(A'length-1 downto 0);
variable carry: std_logic;
begin
carry := '1';
for I in RESULT'reverse_range loop
result(i):=carry xor (not A(i));
carry:=carry and (not A(i));
end loop;
return RESULT;
end;
function HDLi_SUmult (A, B: Std_Logic_Vector) return Std_Logic_Vector is
constant reslen: integer := A'length + B'length;
variable RESULT: Std_Logic_Vector(reslen-1 downto 0);
variable temp: Std_Logic_Vector(reslen-1 downto 0);
variable A1,B1 : Std_Logic_Vector(reslen-1 downto 0);
begin
B1 := HDLi_ZeroExtend(B,reslen);
A1 := HDLi_SignExtend(A,reslen);
RESULT := (others => '0');
for i in 0 to reslen-1 loop
if B1(i) = '1' or B1(i)='H' then
temp := (others => '0');
temp(reslen-1 downto i) := A1(reslen-1-i downto 0);
RESULT := RESULT + temp;
end if;
end loop;
return RESULT(reslen-1 downto 0);
end;
function HDLi_Smult (A, B: Std_Logic_Vector) return Std_Logic_Vector is
constant reslen: integer := A'length + B'length;
variable RESULT: Std_Logic_Vector(reslen-1 downto 0);
variable temp: Std_Logic_Vector(reslen-1 downto 0);
variable A1,B1 : Std_Logic_Vector(reslen-1 downto 0);
begin
B1 := HDLi_SignExtend(B,reslen);
A1 := HDLi_SignExtend(A,reslen);
RESULT := (others => '0');
for i in 0 to reslen-1 loop
if B1(i) = '1' or B1(i)='H' then
temp := (others => '0');
temp(reslen-1 downto i) := A1(reslen-1-i downto 0);
RESULT := RESULT + temp;
end if;
end loop;
return RESULT(reslen-1 downto 0);
end;
function HDLi_Umult (A, B: Std_Logic_Vector) return Std_Logic_Vector is
constant reslen: integer := A'length + B'length;
variable RESULT: Std_Logic_Vector(reslen-1 downto 0);
variable temp: Std_Logic_Vector(reslen-1 downto 0);
variable A1,B1 : Std_Logic_Vector(reslen-1 downto 0);
begin
B1 := HDLi_ZeroExtend(B,reslen);
A1 := HDLi_ZeroExtend(A,reslen);
RESULT := (others => '0');
for i in 0 to reslen-1 loop
if B1(i) = '1' or B1(i)='H' then
temp := (others => '0');
temp(reslen-1 downto i) := A1(reslen-1-i downto 0);
RESULT := RESULT + temp;
end if;
end loop;
return RESULT;
end;
function HDLi_GreyIncr (A: Std_Logic_Vector) return Std_Logic_Vector is
variable L : std_logic_vector(A'range);
variable R : std_logic_vector(A'range);
variable N : std_logic_vector(A'range);
variable S : std_logic_vector(A'range);
begin
L(A'high) := '1';
for index in A'length-2 downto 0 loop
L(index) := A(index+1) xor L(index+1);
end loop;
N(0) := '1';
for index in 1 to (A'length-1) loop
N(index) := not(A(index-1)) and N(index-1);
end loop;
R(0) := '1';
for index in 1 to (A'length-2) loop
R(index) := A(index-1) and N(index-1);
end loop;
R(A'high) := (not(A(A'high)) and A(A'high-1) and N(A'high-1)) or (N(A'high) and A(A'high));
S(0) := L(0);
for index in 1 to (A'length-2) loop
S(index) := A(index) xor (R(index) and L(index-1));
end loop;
S(A'high) := A(A'high) xor R(A'high);
return S;
end;
------------------------------------------------------------------------
function HDLi_AltB_Signed (A, B: Std_Logic_Vector) return Std_Logic is
variable msb: integer;
begin
msb := A'left;
if (A(msb) /= '0' AND A(msb) /= '1') then return 'X'; end if;
if (B(msb) /= '0' AND B(msb) /= '1') then return 'X'; end if;
if (A(msb) = '1' AND B(msb) = '0') then return '1'; end if;
if (A(msb) = '0' AND B(msb) = '1') then return '0'; end if;
for I in A'left - 1 downto 0 loop
if (A(I) /= '0' AND A(I) /= '1') then return 'X'; end if;
if (B(I) /= '0' AND B(I) /= '1') then return 'X'; end if;
if (A(I) = '1' AND B(I) = '0') then return '0'; end if;
if (A(I) = '0' AND B(I) = '1') then return '1'; end if;
end loop;
return '0';
end;
function HDLi_AleB_Signed (A, B: Std_Logic_Vector) return Std_Logic is
variable msb: integer;
begin
msb := A'left;
if (A(msb) /= '0' AND A(msb) /= '1') then return 'X'; end if;
if (B(msb) /= '0' AND B(msb) /= '1') then return 'X'; end if;
if (A(msb) = '1' AND B(msb) = '0') then return '1'; end if;
if (A(msb) = '0' AND B(msb) = '1') then return '0'; end if;
for I in A'left - 1 downto 0 loop
if (A(I) /= '0' AND A(I) /= '1') then return 'X'; end if;
if (B(I) /= '0' AND B(I) /= '1') then return 'X'; end if;
if (A(I) = '1' AND B(I) = '0') then return '0'; end if;
if (A(I) = '0' AND B(I) = '1') then return '1'; end if;
end loop;
return '1';
end;
function HDLi_AgtB_Signed (A, B: Std_Logic_Vector) return Std_Logic is
variable msb: integer;
begin
msb := A'left;
if (A(msb) /= '0' AND A(msb) /= '1') then return 'X'; end if;
if (B(msb) /= '0' AND B(msb) /= '1') then return 'X'; end if;
if (A(msb) = '1' AND B(msb) = '0') then return '0'; end if;
if (A(msb) = '0' AND B(msb) = '1') then return '1'; end if;
for I in A'left - 1 downto 0 loop
if (A(I) /= '0' AND A(I) /= '1') then return 'X'; end if;
if (B(I) /= '0' AND B(I) /= '1') then return 'X'; end if;
if (A(I) = '1' AND B(I) = '0') then return '1'; end if;
if (A(I) = '0' AND B(I) = '1') then return '0'; end if;
end loop;
return '0';
end;
function HDLi_AgeB_Signed (A, B: Std_Logic_Vector) return Std_Logic is
variable msb: integer;
begin
msb := A'left;
if (A(msb) /= '0' AND A(msb) /= '1') then return 'X'; end if;
if (B(msb) /= '0' AND B(msb) /= '1') then return 'X'; end if;
if (A(msb) = '1' AND B(msb) = '0') then return '0'; end if;
if (A(msb) = '0' AND B(msb) = '1') then return '1'; end if;
for I in A'left - 1 downto 0 loop
if (A(I) /= '0' AND A(I) /= '1') then return 'X'; end if;
if (B(I) /= '0' AND B(I) /= '1') then return 'X'; end if;
if (A(I) = '1' AND B(I) = '0') then return '1'; end if;
if (A(I) = '0' AND B(I) = '1') then return '0'; end if;
end loop;
return '1';
end;
function HDLi_AltB_UnSigned (A, B: Std_Logic_Vector) return Std_Logic is
begin
for I in A'left downto 0 loop
if (A(I) /= '0' AND A(I) /= '1') then return 'X'; end if;
if (B(I) /= '0' AND B(I) /= '1') then return 'X'; end if;
if (A(I) = '1' AND B(I) = '0') then return '0'; end if;
if (A(I) = '0' AND B(I) = '1') then return '1'; end if;
end loop;
return '0';
end;
function HDLi_AleB_UnSigned (A, B: Std_Logic_Vector) return Std_Logic is
begin
for I in A'left downto 0 loop
if (A(I) /= '0' AND A(I) /= '1') then return 'X'; end if;
if (B(I) /= '0' AND B(I) /= '1') then return 'X'; end if;
if (A(I) = '1' AND B(I) = '0') then return '0'; end if;
if (A(I) = '0' AND B(I) = '1') then return '1'; end if;
end loop;
return '1';
end;
function HDLi_AgtB_UnSigned (A, B: Std_Logic_Vector) return Std_Logic is
begin
for I in A'left downto 0 loop
if (A(I) /= '0' AND A(I) /= '1') then return 'X'; end if;
if (B(I) /= '0' AND B(I) /= '1') then return 'X'; end if;
if (A(I) = '1' AND B(I) = '0') then return '1'; end if;
if (A(I) = '0' AND B(I) = '1') then return '0'; end if;
end loop;
return '0';
end;
function HDLi_AgeB_UnSigned (A, B: Std_Logic_Vector) return Std_Logic is
begin
for I in A'left downto 0 loop
if (A(I) /= '0' AND A(I) /= '1') then return 'X'; end if;
if (B(I) /= '0' AND B(I) /= '1') then return 'X'; end if;
if (A(I) = '1' AND B(I) = '0') then return '1'; end if;
if (A(I) = '0' AND B(I) = '1') then return '0'; end if;
end loop;
return '1';
end;
function HDLi_AeqB (A, B: Std_Logic_Vector) return Std_Logic is
begin
for I in A'left downto 0 loop
if (A(I) /= '0' AND A(I) /= '1') then return 'X'; end if;
if (B(I) /= '0' AND B(I) /= '1') then return 'X'; end if;
if (A(I) = '1' AND B(I) = '0') then return '0'; end if;
if (A(I) = '0' AND B(I) = '1') then return '0'; end if;
end loop;
return '1';
end;
end HDLI;
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