--------------------------------------------------------------------------------
--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripherals group
--  Bangalore,India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  Module          :  VPB WRAPPER 
--
--  Project         :  VPB Bus interface to USB1.1 device (USBFS22)
--
--  Author          :              
--
--  Description     : The Architecture of VPB_WRAPPER with CTAG isolation cells
--                    This module is a bus wrapper for connecting PVCI interface
--                    to VPB bus
--  Contact address : sanjeev@blr.sc.philips.com
--
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.all;


architecture RTL of VPB_WRAPPER is


-- Signal declarations
signal PSEL_i:    std_logic;              -- Intermediate signal for PSEL
signal PENABLE_i: std_logic;              -- Intermediate signal for PENABLE
signal PWRITE_i:  std_logic;              -- Intermediate signal for PWRITE

-------------------------------------------------------------------
--Changed by St. Gappisch 22.2.01, Introduction of signal psel_reg
--to make USB compatible with VPbus standard
signal psel_reg:  std_logic;   -- registered PSEL register for VPB connection
signal rnw_i:  std_logic;
signal r_data_i:  std_logic_vector(31 downto 0);
-------------------------------------------------------------------
begin
   -------------------------------------------------------------------
   --Changed by St. Gappisch 22.3.01, Generation of r_data_i

    r_data_i <= r_data when  (PENABLE ='1' AND PSEL='1'AND PWRITE='0' )   else (others => '0');
   -------------------------------------------------------------------
  
	PSEL_i <= PSEL;
	PENABLE_i <= PENABLE;
	address <= PADDR;
	PWRITE_i <= PWRITE;
	pvci_reset_n <= PRESETn ;
	w_data <= PWDATA;	
	PRDATA <= r_data;

--  clk          <= PCLK;
--  req          <= PSEL_i xor PENABLE_i;

-----------------------------------------------
--Changed by St. Gappisch 22.2.01, Changed generation 
--of signal 'req' to make interface VPbus compliant
--  req          <= PSEL_i and not PENABLE_i;
-----------------------------------------------
  rnw          <= not PWRITE_i;
  
--  be           <= "1111";

-----------------------------------------------
--Changed by St. Gappisch 22.2.01, Changed generation 
--of signal 'req' to make interface VPbus compliant

   rnw_i <= not PWRITE_i ;

   req_select: process (PSEL_i, PENABLE_i, psel_reg, rnw_i ) 
   begin
      -- read operation
      if (rnw_i= '1') then
        req  <= PSEL_i AND not(psel_reg);
      -- write operation
      else 
	req  <= PSEL_i AND PENABLE_i; 
      end if;
   end process;	 
	 

   psel_q_proc: process(PCLK)
   begin
      if PCLK = '1' and PCLK'event then
          if (PRESETn = '0') then
              psel_reg <= '0';  
          else
              psel_reg <= PSEL_i;  
          end if;
      
      end if;
   end process;
------------------------------------------------

end RTL;