--------------------------------------------------------------------------------
--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore, India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_synchronizer_rtl.vhdl 
--
--  Module          : Synchronizer block
-- 
--  Project         : VPB bus interface to USB 1.1 device 
--
--  Author          :              
-- 
--  Description     : This block provides synchronization for signals crossing
--                    from Fs clock to APB clock. All signals are provided
--                    double FF syncronization.
--
--  Contact address : sanjeev@blr.sc.philips.com
--
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work ;
use work.PCK_GENERAL.all;

library work;
use work.PCK_APB.all; 

architecture RTL of SYNCHRONIZER is

  signal End_Transfer_Q:        one_bit;
  signal End_Transfer_2Q:       one_bit;
  signal End_Transfer_3Q:       one_bit;
  signal Read_Q:                one_bit;
  signal Read_2Q:               one_bit;
  signal Trans_Enable_Q:        one_bit;
  signal Trans_Enable_2Q:       one_bit;
  signal Trans_Enable_3Q:       one_bit;
  signal Trans_Enable_Int:      one_bit; 
  signal USBEp0Intr_Set_Q:      one_bit;
  signal USBEp0Intr_Set_2Q:     one_bit;
  signal USBEp0Intr_Set_3Q:     one_bit;
  signal USBEp1Intr_Set_Q:      one_bit;
  signal USBEp1Intr_Set_2Q:     one_bit;
  signal USBEp1Intr_Set_3Q:     one_bit;
  signal USBEp2Intr_Set_Q:      one_bit;
  signal USBEp2Intr_Set_2Q:     one_bit;
  signal USBEp2Intr_Set_3Q:     one_bit;
  signal USBEp3Intr_Set_Q:      one_bit;
  signal USBEp3Intr_Set_2Q:     one_bit;
  signal USBEp3Intr_Set_3Q:     one_bit;
  signal USBEp4Intr_Set_Q:      one_bit;
  signal USBEp4Intr_Set_2Q:     one_bit;
  signal USBEp4Intr_Set_3Q:     one_bit;
  signal USBEp5Intr_Set_Q:      one_bit;
  signal USBEp5Intr_Set_2Q:     one_bit;
  signal USBEp5Intr_Set_3Q:     one_bit;
  signal USBEp6Intr_Set_Q:      one_bit;
  signal USBEp6Intr_Set_2Q:     one_bit;
  signal USBEp6Intr_Set_3Q:     one_bit;
  signal USBEp7Intr_Set_Q:      one_bit;
  signal USBEp7Intr_Set_2Q:     one_bit;
  signal USBEp7Intr_Set_3Q:     one_bit;
  signal USBDevIntr_Set_Q:      one_bit;
  signal USBDevIntr_Set_2Q:     one_bit;
  signal USBDevIntr_Set_3Q:     one_bit;
  signal FullBuffer_UC_Q:       T_Full;
  signal EndTransfer_Cmd_Q:     one_bit;
  signal EndTransfer_Cmd_2Q:    one_bit;
  signal EndTransfer_Cmd_3Q:    one_bit;
  signal RxError_Q:             boolean;
  signal RxError_2Q:            boolean;
  signal RxError_3Q:            boolean;
  signal USBToggleBuffer_Q:     T_ToggleArray; 
  signal UCToggleBuffer_Q:      T_ToggleArray; 
  signal PI_IsoToggle_Q:        integer range 0 to 1;
  signal PI_IsoToggle_2Q:       integer range 0 to 1;
  signal CmdDataValid_Q:        boolean;
  signal CmdDataValid_2Q:       boolean;
  signal CmdDataValid_3Q:       boolean;
  signal CmdAccept_Q:           boolean;
  signal CmdAccept_2Q:          boolean;
  signal CmdAccept_3Q:          boolean;
  signal start_in_tx_Q:         one_bit;
  signal start_in_tx_2Q:        one_bit;
  signal start_in_tx_I:         one_bit;
  signal FrameIntr_Set_I:       one_bit;  
  signal FrameIntr_Set_Q:       one_bit;  

 begin

  CmdCodeValid_Out   <= CmdCodeValid;
  CommandDataChannel <= CommandData;
  CommandCodeChannel <= CommandCode;
  PI_IsoToggle_Out   <= PI_IsoToggle_2Q;
  
  process(clk) 
    begin
      if(clk'event AND clk = '1') then
         
          -- syncronus reset for all registers
         if(pvci_reset_n = '0') then
            RxCore_Data              <= (others => '0');
            EP_number_out            <= 0;
            If_Busy                  <= false;
            USBEp0IntrSet            <= '0';
            USBEp0Intr_Set_Q         <= '0';
            USBEp0Intr_Set_2Q        <= '0';
            USBEp0Intr_Set_3Q        <= '0';
            USBEp1IntrSet            <= '0';
            USBEp1Intr_Set_Q         <= '0';
            USBEp1Intr_Set_2Q        <= '0';
            USBEp1Intr_Set_3Q        <= '0';
            USBEp2IntrSet            <= '0';
            USBEp2Intr_Set_Q         <= '0';
            USBEp2Intr_Set_2Q        <= '0';
            USBEp2Intr_Set_3Q        <= '0';
            USBEp3IntrSet            <= '0';
            USBEp3Intr_Set_Q         <= '0';
            USBEp3Intr_Set_2Q        <= '0';
            USBEp3Intr_Set_3Q        <= '0';
            USBEp4IntrSet            <= '0';
            USBEp4Intr_Set_Q         <= '0';
            USBEp4Intr_Set_2Q        <= '0';
            USBEp4Intr_Set_3Q        <= '0';
            USBEp5IntrSet            <= '0';
            USBEp5Intr_Set_Q         <= '0';
            USBEp5Intr_Set_2Q        <= '0';
            USBEp5Intr_Set_3Q        <= '0';
            USBEp6IntrSet            <= '0';
            USBEp6Intr_Set_Q         <= '0';
            USBEp6Intr_Set_2Q        <= '0';
            USBEp6Intr_Set_3Q        <= '0';
            USBEp7IntrSet            <= '0';
            USBEp7Intr_Set_Q         <= '0';
            USBEp7Intr_Set_2Q        <= '0';
            USBEp7Intr_Set_3Q        <= '0';
            USBDevIntrSet            <= '0';
            USBDevIntr_Set_Q         <= '0';
            USBDevIntr_Set_2Q        <= '0';
            USBDevIntr_Set_3Q        <= '0';            
            Trans_Enable_Int         <= '0';
            Trans_Enable_Q           <= '0';
            Trans_Enable_2Q          <= '0';
            Trans_Enable_3Q          <= '0';
            Read_Data                <= '0';
            Read_Q                   <= '0';
            Read_2Q                  <= '0';
            End_Transfer_D           <= '0';
            End_Transfer_Q           <= '0';
            End_Transfer_2Q          <= '0';
            End_Transfer_3Q          <= '0';
            EndTransfer_Cmd_D        <= '0';
            EndTransfer_Cmd_Q        <= '0';
            EndTransfer_Cmd_2Q       <= '0';
            EndTransfer_Cmd_3Q       <= '0';
            RxError_Out              <= false;
            RxError_Q                <= false;
            RxError_2Q               <= false;
            RxError_3Q               <= false;
            USBToggleBuffer_Q        <= (others => 0);
            USBToggleBuffer_Out      <= (others => 0);
            UCToggleBuffer_Q         <= (others => 0);
            UCToggleBuffer_Out       <= (others => 0);
            FullBuffer_UC_Q          <= (others => (others => false));
            FullBuffer_EP            <= (others => (others => false));
            PI_IsoToggle_2Q          <= 0;
            PI_IsoToggle_Q           <= 0;
            CmdDataValid_Q           <= false;
            CmdDataValid_2Q          <= false;
            CmdDataValid_3Q          <= false;
            CmdAccept_Q              <= false;
            CmdAccept_2Q             <= false;
            CmdAccept_3Q             <= false;
            start_in_tx_Q            <= '0';
            start_in_tx_2Q           <= '0';
            start_in_tx_I            <= '0';
            TxDest_Endp              <= 0;
            start_in_tx              <= '0';
            FrameIntr_Set_I          <= '0';
            FrameIntr_Set_Q          <= '0';
            FrameIntr_Set            <= '0';

         else
            
            -- Read in to GIF from PI handler.
            if(Trans_Enable_Int = '1' ) then
               RxCore_Data     <= Data_Out;
               EP_number_out   <= EP_number;
               If_Busy         <= true;
            end if;  

            -- Edge Detection with Double Flip-Flop for Trans_Enable
            Trans_Enable_Q   <= Trans_Enable;
            Trans_Enable_2Q  <= Trans_Enable_Q;
            Trans_Enable_3Q  <= Trans_Enable_2Q;
            Trans_Enable_Int <= Trans_Enable_2Q and not Trans_Enable_3Q;

            -- Edge detection with Double Flip-Flop for Read_Write
            Read_Q    <= Read;
            Read_2Q   <= Read_Q;
            Read_Data <= Read_Q and not Read_2Q;

            --Edge detection with Double Flip-Flop for End_Transfer.
            End_Transfer_Q   <= End_Transfer;
            End_Transfer_2Q  <= End_Transfer_Q;
            End_Transfer_3Q  <= End_Transfer_2Q;
            End_Transfer_D   <= End_Transfer_2Q and not End_Transfer_3Q;

            -- Edge detection with Double Flip-Flop for EndTransfer_Cmd
            EndTransfer_Cmd_Q  <= EndTransfer_Cmd;
            EndTransfer_Cmd_2Q <= EndTransfer_Cmd_Q;
            EndTransfer_Cmd_3Q <= EndTransfer_Cmd_2Q;
            EndTransfer_Cmd_D  <= EndTransfer_Cmd_2Q and not EndTransfer_Cmd_3Q;

            -- Edge detection with Double Flip-Flop for USBEp0Intr_Set 
            USBEp0Intr_Set_Q  <= USBEp0Intr_Set;
            USBEp0Intr_Set_2Q <= USBEp0Intr_Set_Q;
            USBEp0Intr_Set_3Q <= USBEp0Intr_Set_2Q;
            USBEp0IntrSet     <= USBEp0Intr_Set_2Q and not USBEp0Intr_Set_3Q;

            -- Edge detection with Double Flip-Flop for USBEp1Intr_Set 
            USBEp1Intr_Set_Q  <= USBEp1Intr_Set;
            USBEp1Intr_Set_2Q <= USBEp1Intr_Set_Q;
            USBEp1Intr_Set_3Q <= USBEp1Intr_Set_2Q;
            USBEp1IntrSet     <= USBEp1Intr_Set_2Q and not USBEp1Intr_Set_3Q;

            -- Edge detection with Double Flip-Flop for USBEp2Intr_Set 
            USBEp2Intr_Set_Q  <= USBEp2Intr_Set;
            USBEp2Intr_Set_2Q <= USBEp2Intr_Set_Q;
            USBEp2Intr_Set_3Q <= USBEp2Intr_Set_2Q;
            USBEp2IntrSet     <= USBEp2Intr_Set_2Q and not USBEp2Intr_Set_3Q;

            -- Edge detection with Double Flip-Flop for USBEp3Intr_Set 
            USBEp3Intr_Set_Q  <= USBEp3Intr_Set;
            USBEp3Intr_Set_2Q <= USBEp3Intr_Set_Q;
            USBEp3Intr_Set_3Q <= USBEp3Intr_Set_2Q;
            USBEp3IntrSet     <= USBEp3Intr_Set_2Q and not USBEp3Intr_Set_3Q;

            -- Edge detection with Double Flip-Flop for USBEp4Intr_Set 
            USBEp4Intr_Set_Q  <= USBEp4Intr_Set;
            USBEp4Intr_Set_2Q <= USBEp4Intr_Set_Q;
            USBEp4Intr_Set_3Q <= USBEp4Intr_Set_2Q;
            USBEp4IntrSet     <= USBEp4Intr_Set_2Q and not USBEp4Intr_Set_3Q;

            -- Edge detection with Double Flip-Flop for USBEp5Intr_Set 
            USBEp5Intr_Set_Q  <= USBEp5Intr_Set;
            USBEp5Intr_Set_2Q <= USBEp5Intr_Set_Q;
            USBEp5Intr_Set_3Q <= USBEp5Intr_Set_2Q;
            USBEp5IntrSet     <= USBEp5Intr_Set_2Q and not USBEp5Intr_Set_3Q;

            -- Edge detection with Double Flip-Flop for USBEp6Intr_Set 
            USBEp6Intr_Set_Q  <= USBEp6Intr_Set;
            USBEp6Intr_Set_2Q <= USBEp6Intr_Set_Q;
            USBEp6Intr_Set_3Q <= USBEp6Intr_Set_2Q;
            USBEp6IntrSet     <= USBEp6Intr_Set_2Q and not USBEp6Intr_Set_3Q;

            -- Edge detection with Double Flip-Flop for USBEp7Intr_Set 
            USBEp7Intr_Set_Q  <= USBEp7Intr_Set;
            USBEp7Intr_Set_2Q <= USBEp7Intr_Set_Q;
            USBEp7Intr_Set_3Q <= USBEp7Intr_Set_2Q;
            USBEp7IntrSet     <= USBEp7Intr_Set_2Q and not USBEp7Intr_Set_3Q;

            -- Edge detection with Double Flip-Flop for USBDevIntr_Set 
            USBDevIntr_Set_Q  <= USBDevIntr_Set;
            USBDevIntr_Set_2Q <= USBDevIntr_Set_Q;
            USBDevIntr_Set_3Q <= USBDevIntr_Set_2Q;
            USBDevIntrSet     <= USBDevIntr_Set_2Q and not USBDevIntr_Set_3Q;

            -- Rx DMA Valid Data
            FullBuffer_UC_Q   <= FullBuffer_UC;
            FullBuffer_EP     <= FullBuffer_UC_Q;

            -- USB Toggle 
            USBToggleBuffer_Q   <= USBToggleBuffer; 
            USBToggleBuffer_Out <= USBToggleBuffer_Q; 

            -- UC Toggle
            UCToggleBuffer_Q    <= UCToggleBuffer;
            UCToggleBuffer_Out  <= UCToggleBuffer_Q;

            -- Edge detection for RxError.
            RxError_Q   <= RxError;
            RxError_2Q  <= RxError_Q;
            RxError_3Q  <= RxError_2Q;
            RxError_Out <= RxError_2Q and not RxError_3Q;

            -- IsoToggle
            PI_IsoToggle_Q   <= PI_IsoToggle; 
            PI_IsoToggle_2Q  <= PI_IsoToggle_Q;

            -- Generation of Frame interrupt
            if(PI_IsoToggle_2Q = 0) then
               FrameIntr_Set_I <= '0';
            else
               FrameIntr_Set_I <= '1';
            end if;
            FrameIntr_Set_Q <= FrameIntr_Set_I ;
            FrameIntr_Set   <= (FrameIntr_Set_Q and not FrameIntr_Set_I ) or (not FrameIntr_Set_Q and FrameIntr_Set_I);

            -- Command accept
            CmdAccept_Q   <= CmdAccept;
            CmdAccept_2Q  <= CmdAccept_Q;
            CmdAccept_3Q  <= CmdAccept_2Q;
            CmdAccept_Out <= CmdAccept_2Q and not CmdAccept_3Q;

            -- Command data valid
            CmdDataValid_Q   <= CmdDataValid; 
            CmdDataValid_2Q  <= CmdDataValid_Q;
            CmdDataValid_3Q  <= CmdDataValid_2Q;
            CmdDataValid_Out <= CmdDataValid_2Q and not CmdDataValid_3Q;
 
            -- start_in_tx
            start_in_tx_Q  <= reg_ram_read;
            start_in_tx_2Q <= start_in_tx_Q;
            start_in_tx_I  <= start_in_tx_Q and not start_in_tx_2Q;
  
            if(start_in_tx_I = '1') then
               start_in_tx <= '1';
               TxDest_Endp <= reg_ram_tag;
            else
               start_in_tx <= '0';
            end if;
          
            -- Resetting of if_busy
            if(RxDataAccepted) then
               If_Busy   <= false;
            end if;
          
         end if;
      end if;
  end process;
end RTL;