--------------------------------------------------------------------------------
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore, India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_usb_cntrl_rtl.vhdl 
--  
--  Module          : USB controller
--
--  Project         : VPB bus interface to USB 1.1 device (USBFS22)
--
--  Author          :
--
--  Description     : The architecture of USB controller module
--                    This block has a interrupt controller and all the interface
--                    registers.
--
--  Contact address : sanjeev@blr.sc.philips.com
--
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_APB.all;

architecture RTL of USB_CNTRL is

constant N_intrbits : integer := 13;
signal Cmd_Code_Reg:           eleven_bits;
signal Cmd_Data_Reg:           byte;
signal Receive_Data_Reg:       four_bytes;
signal Tramsmt_Data_Reg:       four_bytes;
signal Intr_Status_Reg:        twenty_bits;
signal Intr_Enable_Reg:        fourteen_bits;
signal TxPkt_Lngth_Reg:        ten_bits; 
signal RxPkt_Lngth_Reg:        eleven_bits;
signal Usb_Cntrl_Reg:          six_bits;
signal Fiq_Sel_Reg:            three_bits;

signal Cmd_Code_Reg_Full:      one_bit;
signal Cmd_Data_Reg_full:      one_bit;
signal Receive_Data_Reg_Full:  one_bit;
signal Trnsmt_Data_Reg_Full:   one_bit;

signal Read_Enable:            one_bit;
signal Read_Enable_Q:          one_bit;
signal Write_Enable:           one_bit;
signal Write_Enable_Q:         one_bit;
signal CmdCodeEmpty_IntrSet:   one_bit;
signal CmdCodeValid_I:         boolean;
signal CmdDataFull_IntrSet:    one_bit; 
signal EndPaktOut_IntrSet:     one_bit;
signal EndPaktIn_IntrSet:      one_bit;
signal Tx_Pkt_End_I:           one_bit;
signal Tx_Pkt_End_Q:           one_bit;
signal Rx_Pkt_End_I:           one_bit;
signal Read_Enable_I:          one_bit;

begin
  Endpoint_Nr  <= to_integer(Wr_Data(5 downto 2)) when Write_Usb_Cntrl = '1' 
		  else to_integer(Usb_Cntrl_Reg(5 downto 2));
  RxRam_Read  <=  not Receive_Data_Reg_Full and Read_Enable;
  TxRam_Write <=  Trnsmt_Data_Reg_Full and Usb_Cntrl_Reg(1);
  DataToRam    <=  Tramsmt_Data_Reg;
  Read_Enable  <=  Wr_data(0) when Write_Usb_Cntrl = '1' else
		   Read_Enable_I;
  CmdCodeValid <= Cmd_Code_Reg_Full = '1' ;
  CommandCode  <= Cmd_Code_Reg;
  Tx_Pkt_End   <= Tx_Pkt_End_Q;
  Receive_Data_Reg <= DataFromRam;
  Rx_Pkt_End    <=  Rx_Pkt_End_I;

  process(clk)
    
    ------------------------------------------------------------------------------
    procedure  InterruptController is
      variable irqstatus_var:    one_bit;
      variable fiqstatus_var:    one_bit;
    begin
       -- Writing into Interrupt Enable Register
       if(Write_Intr_Enable = '1') then
          Intr_Enable_Reg <= Wr_Data(13 downto 0);
       end if;
       -- Clearing of the status Register
       if(Write_Intr_Clear = '1') then
          for i in 0 to N_intrbits loop
             if(Wr_Data(i) = '1') then
                Intr_Status_Reg(i) <= '0';
             end if;
          end loop;
       end if;
       -- Setting the interrupts for debug purposes
       if(Write_Intr_Set = '1') then
          for i in 0 to N_intrbits loop
             if(Wr_Data(i) = '1') then
                Intr_Status_Reg(i)   <= '1';
             end if;
          end loop;
       end if;
       
       -- Update status register when there is flag is set
       if(FrameIntr_Set = '1') then
          Intr_Status_Reg(IntrNo_Frame) <= '1';
       end if; 
       --if(UsbCoreIntrSet = '1') then
       --   Intr_Status_Reg(IntrNo_USB_Core) <= '1';
          -- Set '1' in Int Status register's EP status bits when an IN token is NAKed and
	  -- Buffer is full
          -- Bit  8: EP1 IN
          -- Bit  9: EP3 IN
          -- Bit 10: EP5 IN
          -- Bit 11: EP7 IN
       if(UsbEp0IntrSet = '1') then
          Intr_Status_Reg(IntrNo_USB_Ep0) <= '1';
       end if;
       if(UsbEp1IntrSet = '1') then 
          Intr_Status_Reg(IntrNo_USB_Ep1) <= '1';
	  if(FullBuffer_EP(1)(0)) then
	     Intr_Status_Reg(Ep1_NAK) <= '1';
          else
	     Intr_Status_Reg(Ep1_NAK) <= '0';
          end if;
       end if;
       if(UsbEp2IntrSet = '1') then
          Intr_Status_Reg(IntrNo_USB_Ep2) <= '1';
       end if;
       if(UsbEp3IntrSet = '1') then
          Intr_Status_Reg(IntrNo_USB_Ep3) <= '1';
	  if(FullBuffer_EP(3)(0)) then
	     Intr_Status_Reg(Ep3_NAK) <= '1';
          else
	     Intr_Status_Reg(Ep3_NAK) <= '0';
          end if;
       end if;
       if(UsbEp4IntrSet = '1') then
          Intr_Status_Reg(IntrNo_USB_Ep4) <= '1';
       end if;
       if(UsbEp5IntrSet = '1') then
          Intr_Status_Reg(IntrNo_USB_Ep5) <= '1';
	  if(FullBuffer_EP(5)(0)) then
	     Intr_Status_Reg(Ep5_NAK) <= '1';
          else
	     Intr_Status_Reg(Ep5_NAK) <= '0';
          end if;
       end if;
       if(UsbEp6IntrSet = '1') then
          Intr_Status_Reg(IntrNo_USB_Ep6) <= '1';
       end if;
       if(UsbEp7IntrSet = '1') then
          Intr_Status_Reg(IntrNo_USB_Ep7) <= '1';
	  if(FullBuffer_EP(7)(USBToggleBuffer_Out(7))) then
	     Intr_Status_Reg(Ep7_NAK) <= '1';
          else
	     Intr_Status_Reg(Ep7_NAK) <= '0';
          end if;
       end if;
       if(UsbDevIntrSet = '1') then
          Intr_Status_Reg(IntrNo_USB_Dev) <= '1';
       end if;
       
       --end if;
       if(CmdCodeEmpty_IntrSet = '1') then
          Intr_Status_Reg(IntrNo_CmdCodeReg_Empty) <= '1'; 
       end if;    
       if(CmdDataFull_IntrSet = '1') then
          Intr_Status_Reg(IntrNo_CmdDataReg_Full) <= '1'; 
       end if;     
       if(EndPaktOut_IntrSet = '1') then
          Intr_Status_Reg(IntrNo_OUT_EndOfPacket) <= '1';
       end if;
       if(EndPaktIn_IntrSet = '1') then
          Intr_Status_Reg(IntrNo_IN_EndOfPacket) <= '1';
       end if;   
       irqstatus_var := '0';
       
       -- Select FIQ interrupt from Frame_Interrupt, EP6_Interrupt and Ep7_Interrupt
       -- depending on the flag that is set in Fiq_Sel_Reg
       case Fiq_Sel_Reg is
          when "001" => 
               fiqstatus_var := Intr_Status_Reg(0) and Intr_Enable_Reg(0);
               for i in 1 to N_intrbits loop
                   irqstatus_var := irqstatus_var or (Intr_Status_Reg(i) and Intr_Enable_Reg(i));
               end loop;
          when "010" =>
               fiqstatus_var := Intr_Status_Reg(7) and Intr_Enable_Reg(7);
               for i in 0 to 6 loop
                   irqstatus_var := irqstatus_var or (Intr_Status_Reg(i) and Intr_Enable_Reg(i));
               end loop;
               for i in 8 to N_intrbits loop
                   irqstatus_var := irqstatus_var or (Intr_Status_Reg(i) and Intr_Enable_Reg(i));
               end loop;
          when "100" =>
               fiqstatus_var := Intr_Status_Reg(8) and Intr_Enable_Reg(8);
               for i in 0 to 7 loop
                   irqstatus_var := irqstatus_var or (Intr_Status_Reg(i) and Intr_Enable_Reg(i));
               end loop;
               for i in 9 to N_intrbits loop
                   irqstatus_var := irqstatus_var or (Intr_Status_Reg(i) and Intr_Enable_Reg(i));