Release 6.2i Map G.28Xilinx Mapping Report File for Design 'top'Design Information------------------Command Line   : D:/install/Xilinx/bin/nt/map.exe -intstyle ise -p
xc3s400-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd
top.pcf Target Device  : x3s400Target Package : pq208Target Speed   : -4Mapper Version : spartan3 -- $Revision: 1.16.8.1 $Mapped Date    : Fri Dec 15 10:35:24 2006Design Summary--------------Number of errors:      0Number of warnings:    0Logic Utilization:  Number of Slice Flip Flops:          72 out of   7,168    1%  Number of 4 input LUTs:              73 out of   7,168    1%Logic Distribution:  Number of occupied Slices:                           56 out of   3,584    1%    Number of Slices containing only related logic:      56 out of      56  100%    Number of Slices containing unrelated logic:          0 out of      56    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:             98 out of   7,168    1%  Number used as logic:                 73  Number used as a route-thru:          25  Number of bonded IOBs:               45 out of     141   31%  Number of GCLKs:                     1 out of       8   12%Total equivalent gate count for design:  1,167Additional JTAG gate count for IOBs:  2,160Peak Memory Usage:  74 MBNOTES:   Related logic is defined as being logic that shares connectivity -   e.g. two LUTs are "related" if they share common inputs.   When assembling slices, Map gives priority to combine logic that   is related.  Doing so results in the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin   packing unrelated logic into a slice once 99% of the slices are   occupied through related logic packing.   Note that once logic distribution reaches the 99% level through   related logic packing, this does not mean the device is completely   utilized.  Unrelated logic packing will then begin, continuing until   all usable LUTs and FFs are occupied.  Depending on your timing   budget, increased levels of unrelated logic packing may adversely   affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| CE_SRAM                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || LB_SRAM                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || OE_SRAM                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || UB_SRAM                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || WE_SRAM                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<0>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<1>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<2>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<3>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<4>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<5>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<6>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<7>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<8>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<9>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<10>                      | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<11>                      | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<12>                      | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<13>                      | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<14>                      | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || addr_SRAM<15>                      | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || clk                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || data_SRAM<0>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || data_SRAM<1>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || data_SRAM<2>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || data_SRAM<3>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || data_SRAM<4>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || data_SRAM<5>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || data_SRAM<6>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || data_SRAM<7>                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || empty_flag                         | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || fifoaddr<0>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || fifoaddr<1>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || fifodata<0>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || fifodata<1>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || fifodata<2>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || fifodata<3>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || fifodata<4>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || fifodata<5>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || fifodata<6>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || fifodata<7>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || led                                | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || reset                              | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || sloe                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || slrd                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 45Number of Equivalent Gates for Design = 1,167Number of RPM Macros = 0Number of Hard Macros = 0DCIRESETs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DCMs = 0GCLKs = 1ICAPs = 018X18 Multipliers = 0Block RAMs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 16IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 45Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFXs = 0MULTANDs = 04 input LUTs used as Route-Thrus = 254 input LUTs = 73Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 16Slice Flip Flops = 72SliceMs = 0SliceLs = 56Slices = 56Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 2Number of LUT signals with 1 load = 64NGM Average fanout of LUT = 2.36NGM Maximum fanout of LUT = 26NGM Average fanin for LUT = 3.7123Number of LUT symbols = 73Number of IPAD symbols = 11Number of IBUF symbols = 11