JDF G
// Created by Project Navigator ver 1.0
PROJECT FPGA
DESIGN fpga
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s400
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE top.vhdl
DEPASSOC top ucf.ucf
[Normal]
xilxBitgCfg_GenOpt_LogicAllocFile=xstvhd, spartan3, Implementation.t_bitFile, 1161770119, False
xilxBitgCfg_GenOpt_MaskFile=xstvhd, spartan3, Implementation.t_bitFile, 1161651806, True
xilxBitgCfg_GenOpt_ReadBack_Spartan3=xstvhd, spartan3, Implementation.t_bitFile, 1161651806, True
xilxBitgReadBk_GenBitStr=xstvhd, spartan3, Implementation.t_bitFile, 1161770119, False
[STRATEGY-LIST]
Normal=True