# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		FPGA_AM_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name TOP_LEVEL_ENTITY FPGA_AM_TEST
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:53:01  AUGUST 14, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 8.0
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE source/FPGA_AM.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_location_assignment PIN_130 -to DA_CLK
set_location_assignment PIN_17 -to LCK
set_location_assignment PIN_77 -to RESULT[9]
set_location_assignment PIN_78 -to RESULT[8]
set_location_assignment PIN_83 -to RESULT[7]
set_location_assignment PIN_100 -to RESULT[6]
set_location_assignment PIN_124 -to RESULT[5]
set_location_assignment PIN_123 -to RESULT[4]
set_location_assignment PIN_126 -to RESULT[3]
set_location_assignment PIN_125 -to RESULT[2]
set_location_assignment PIN_128 -to RESULT[1]
set_location_assignment PIN_127 -to RESULT[0]
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name VHDL_FILE source/CARRIER.vhd
set_global_assignment -name VHDL_FILE source/MODEM.vhd
set_global_assignment -name VHDL_FILE BU_MA.vhd
set_global_assignment -name BDF_FILE source/FPGA_AM_TEST.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE source/FPGA_AM.vwf
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name VHDL_FILE source/test.vhd
set_location_assignment PIN_16 -to CLK_20M
set_location_assignment PIN_122 -to fsk_data
set_global_assignment -name MIF_FILE source/FPGA_AM_rom.mif
set_global_assignment -name VHDL_FILE source/CARRIER_KHZ507.vhd
set_global_assignment -name MIF_FILE source/FPGA_AM_rom_98.mif
set_global_assignment -name MIF_FILE source/FPGA_AM_394.mif