Simulator report for FPGA_AM
Thu Aug 14 16:44:09 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ALTSYNCRAM
  6. Coverage Summary
  7. Complete 1/0-Value Coverage
  8. Missing 1-Value Coverage
  9. Missing 0-Value Coverage
 10. Simulator INI Usage
 11. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 1.0 us       ;
; Simulation Netlist Size     ; 237 nodes    ;
; Simulation Coverage         ;      81.96 % ;
; Total Number of Transitions ; 117083       ;
; Simulation Breakpoints      ; 0            ;
; Family                      ; Cyclone      ;
+-----------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                              ;
+--------------------------------------------------------------------------------------------+--------------------+---------------+
; Option                                                                                     ; Setting            ; Default Value ;
+--------------------------------------------------------------------------------------------+--------------------+---------------+
; Simulation mode                                                                            ; Functional         ; Timing        ;
; Start time                                                                                 ; 0 ns               ; 0 ns          ;
; Simulation results format                                                                  ; CVWF               ;               ;
; Vector input source                                                                        ; source/FPGA_AM.vwf ;               ;
; Add pins automatically to simulation output waveforms                                      ; On                 ; On            ;
; Check outputs                                                                              ; Off                ; Off           ;
; Report simulation coverage                                                                 ; On                 ; On            ;
; Display complete 1/0 value coverage report                                                 ; On                 ; On            ;
; Display missing 1-value coverage report                                                    ; On                 ; On            ;
; Display missing 0-value coverage report                                                    ; On                 ; On            ;
; Detect setup and hold time violations                                                      ; Off                ; Off           ;
; Detect glitches                                                                            ; Off                ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off                ; Off           ;
; Generate Signal Activity File                                                              ; Off                ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off                ; Off           ;