{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 27 15:42:45 2008 " "Info: Processing started: Wed Aug 27 15:42:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off FPGA_AM -c FPGA_AM " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off FPGA_AM -c FPGA_AM" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "FPGA_AM EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"FPGA_AM\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "altpll0_200M:inst6\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"altpll0_200M:inst6\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll0_200M:inst6\|altpll:altpll_component\|_clk0 4 1 0 0 " "Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll0_200M:inst6\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } { "altpll0_200M.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/altpll0_200M.vhd" 129 0 0 } } { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 64 -312 -72 224 "inst6" "" } } } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "312 Top " "Info: Previous placement does not exist for 312 of 312 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 12 " "Info: Pin ~nCSO~ is reserved at location 12" {  } { { "i:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "i:/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 25 " "Info: Pin ~ASDO~ is reserved at location 25" {  } { { "i:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "i:/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "LCK " "Info: Promoted signal \"LCK\" to use global clock" {  } { { "i:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "i:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCK" } { 0 "LCK" } } } } { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 120 -520 -352 136 "LCK" "" } } } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCK } "NODE_NAME" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCK } "NODE_NAME" } } { "i:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "i:/altera/72/quartus/bin/pin_planner.ppl" { LCK } } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "altpll0_200M:inst6\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "i:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "i:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "altpll0_200M:inst6\|altpll:altpll_component\|_clk0" } } } } { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 64 -312 -72 224 "inst6" "" } } } } { "altpll.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 585 3 0 } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0_200M:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0_200M:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0 "" 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}