{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLK_20M " "Warning: Node \"CLK_20M\" is assigned to location or region, but does not exist in design" {  } { { "i:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "i:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_20M" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.419 ns register register " "Info: Estimated most critical path is register to register delay of 3.419 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CARRIER_507:inst16\|PHASE_WORD\[1\] 1 REG LAB_X15_Y3 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y3; Fanout = 14; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[1\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.575 ns) 1.281 ns CARRIER_507:inst16\|Add0~135COUT1 2 COMB LAB_X16_Y3 2 " "Info: 2: + IC(0.706 ns) + CELL(0.575 ns) = 1.281 ns; Loc. = LAB_X16_Y3; Fanout = 2; COMB Node = 'CARRIER_507:inst16\|Add0~135COUT1'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.281 ns" { CARRIER_507:inst16|PHASE_WORD[1] CARRIER_507:inst16|Add0~135COUT1 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.361 ns CARRIER_507:inst16\|Add0~137COUT1 3 COMB LAB_X16_Y3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.361 ns; Loc. = LAB_X16_Y3; Fanout = 2; COMB Node = 'CARRIER_507:inst16\|Add0~137COUT1'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { CARRIER_507:inst16|Add0~135COUT1 CARRIER_507:inst16|Add0~137COUT1 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.441 ns CARRIER_507:inst16\|Add0~139COUT1 4 COMB LAB_X16_Y3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.441 ns; Loc. = LAB_X16_Y3; Fanout = 2; COMB Node = 'CARRIER_507:inst16\|Add0~139COUT1'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { CARRIER_507:inst16|Add0~137COUT1 CARRIER_507:inst16|Add0~139COUT1 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.699 ns CARRIER_507:inst16\|Add0~141 5 COMB LAB_X16_Y3 4 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.699 ns; Loc. = LAB_X16_Y3; Fanout = 4; COMB Node = 'CARRIER_507:inst16\|Add0~141'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { CARRIER_507:inst16|Add0~139COUT1 CARRIER_507:inst16|Add0~141 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.378 ns CARRIER_507:inst16\|Add0~142 6 COMB LAB_X16_Y3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.378 ns; Loc. = LAB_X16_Y3; Fanout = 1; COMB Node = 'CARRIER_507:inst16\|Add0~142'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { CARRIER_507:inst16|Add0~141 CARRIER_507:inst16|Add0~142 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.738 ns) 3.419 ns CARRIER_507:inst16\|PHASE_WORD\[5\] 7 REG LAB_X15_Y3 14 " "Info: 7: + IC(0.303 ns) + CELL(0.738 ns) = 3.419 ns; Loc. = LAB_X15_Y3; Fanout = 14; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[5\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.041 ns" { CARRIER_507:inst16|Add0~142 CARRIER_507:inst16|PHASE_WORD[5] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.410 ns ( 70.49 % ) " "Info: Total cell delay = 2.410 ns ( 70.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 29.51 % ) " "Info: Total interconnect delay = 1.009 ns ( 29.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.419 ns" { CARRIER_507:inst16|PHASE_WORD[1] CARRIER_507:inst16|Add0~135COUT1 CARRIER_507:inst16|Add0~137COUT1 CARRIER_507:inst16|Add0~139COUT1 CARRIER_507:inst16|Add0~141 CARRIER_507:inst16|Add0~142 CARRIER_507:inst16|PHASE_WORD[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X14_Y0 X27_Y14 " "Info: Peak interconnect usage is 4% of the available device resources in the region that extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "J:/FPGA/my_exercises/AM/project/FPGA_AM.fit.smsg " "Info: Generated suppressed messages file J:/FPGA/my_exercises/AM/project/FPGA_AM.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 27 15:42:52 2008 " "Info: Processing ended: Wed Aug 27 15:42:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}