{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0_200M:inst6\|altpll:altpll_component\|_clk0 register CARRIER_507:inst16\|PHASE_WORD\[1\] register CARRIER_507:inst16\|PHASE_WORD\[7\] 1.368 ns " "Info: Slack time is 1.368 ns for clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" between source register \"CARRIER_507:inst16\|PHASE_WORD\[1\]\" and destination register \"CARRIER_507:inst16\|PHASE_WORD\[7\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.739 ns + Largest register register " "Info: + Largest register to register requirement is 4.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 3.167 ns " "Info: + Latch edge is 3.167 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0_200M:inst6\|altpll:altpll_component\|_clk0 5.000 ns -1.833 ns  50 " "Info: Clock period of Destination clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0_200M:inst6\|altpll:altpll_component\|_clk0 5.000 ns -1.833 ns  50 " "Info: Clock period of Source clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0_200M:inst6\|altpll:altpll_component\|_clk0 destination 2.279 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" to destination register is 2.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0_200M:inst6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 27; CLK Node = 'altpll0_200M:inst6\|altpll:altpll_component\|_clk0'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0_200M:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(0.711 ns) 2.279 ns CARRIER_507:inst16\|PHASE_WORD\[7\] 2 REG LC_X15_Y3_N9 6 " "Info: 2: + IC(1.568 ns) + CELL(0.711 ns) = 2.279 ns; Loc. = LC_X15_Y3_N9; Fanout = 6; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[7\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[7] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 31.20 % ) " "Info: Total cell delay = 0.711 ns ( 31.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.568 ns ( 68.80 % ) " "Info: Total interconnect delay = 1.568 ns ( 68.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[7] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[7] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0_200M:inst6\|altpll:altpll_component\|_clk0 source 2.279 ns - Longest register " "Info: - Longest clock path from clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" to source register is 2.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0_200M:inst6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 27; CLK Node = 'altpll0_200M:inst6\|altpll:altpll_component\|_clk0'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0_200M:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(0.711 ns) 2.279 ns CARRIER_507:inst16\|PHASE_WORD\[1\] 2 REG LC_X15_Y3_N7 6 " "Info: 2: + IC(1.568 ns) + CELL(0.711 ns) = 2.279 ns; Loc. = LC_X15_Y3_N7; Fanout = 6; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[1\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 31.20 % ) " "Info: Total cell delay = 0.711 ns ( 31.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.568 ns ( 68.80 % ) " "Info: Total interconnect delay = 1.568 ns ( 68.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[7] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[7] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[7] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[7] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.371 ns - Longest register register " "Info: - Longest register to register delay is 3.371 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CARRIER_507:inst16\|PHASE_WORD\[1\] 1 REG LC_X15_Y3_N7 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y3_N7; Fanout = 6; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[1\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.807 ns) + CELL(0.423 ns) 1.230 ns CARRIER_507:inst16\|Add0~135 2 COMB LC_X16_Y3_N1 2 " "Info: 2: + IC(0.807 ns) + CELL(0.423 ns) = 1.230 ns; Loc. = LC_X16_Y3_N1; Fanout = 2; COMB Node = 'CARRIER_507:inst16\|Add0~135'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.230 ns" { CARRIER_507:inst16|PHASE_WORD[1] CARRIER_507:inst16|Add0~135 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.308 ns CARRIER_507:inst16\|Add0~137 3 COMB LC_X16_Y3_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.308 ns; Loc. = LC_X16_Y3_N2; Fanout = 2; COMB Node = 'CARRIER_507:inst16\|Add0~137'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { CARRIER_507:inst16|Add0~135 CARRIER_507:inst16|Add0~137 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.386 ns CARRIER_507:inst16\|Add0~139 4 COMB LC_X16_Y3_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.386 ns; Loc. = LC_X16_Y3_N3; Fanout = 2; COMB Node = 'CARRIER_507:inst16\|Add0~139'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { CARRIER_507:inst16|Add0~137 CARRIER_507:inst16|Add0~139 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.564 ns CARRIER_507:inst16\|Add0~141 5 COMB LC_X16_Y3_N4 4 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.564 ns; Loc. = LC_X16_Y3_N4; Fanout = 4; COMB Node = 'CARRIER_507:inst16\|Add0~141'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { CARRIER_507:inst16|Add0~139 CARRIER_507:inst16|Add0~141 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.185 ns CARRIER_507:inst16\|Add0~146 6 COMB LC_X16_Y3_N7 1 " "Info: 6: + IC(0.000 ns) + CELL(0.621 ns) = 2.185 ns; Loc. = LC_X16_Y3_N7; Fanout = 1; COMB Node = 'CARRIER_507:inst16\|Add0~146'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { CARRIER_507:inst16|Add0~141 CARRIER_507:inst16|Add0~146 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.478 ns) 3.371 ns CARRIER_507:inst16\|PHASE_WORD\[7\] 7 REG LC_X15_Y3_N9 6 " "Info: 7: + IC(0.708 ns) + CELL(0.478 ns) = 3.371 ns; Loc. = LC_X15_Y3_N9; Fanout = 6; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[7\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.186 ns" { CARRIER_507:inst16|Add0~146 CARRIER_507:inst16|PHASE_WORD[7] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.856 ns ( 55.06 % ) " "Info: Total cell delay = 1.856 ns ( 55.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.515 ns ( 44.94 % ) " "Info: Total interconnect delay = 1.515 ns ( 44.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.371 ns" { CARRIER_507:inst16|PHASE_WORD[1] CARRIER_507:inst16|Add0~135 CARRIER_507:inst16|Add0~137 CARRIER_507:inst16|Add0~139 CARRIER_507:inst16|Add0~141 CARRIER_507:inst16|Add0~146 CARRIER_507:inst16|PHASE_WORD[7] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.371 ns" { CARRIER_507:inst16|PHASE_WORD[1] {} CARRIER_507:inst16|Add0~135 {} CARRIER_507:inst16|Add0~137 {} CARRIER_507:inst16|Add0~139 {} CARRIER_507:inst16|Add0~141 {} CARRIER_507:inst16|Add0~146 {} CARRIER_507:inst16|PHASE_WORD[7] {} } { 0.000ns 0.807ns 0.000ns 0.000ns 0.000ns 0.000ns 0.708ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[7] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[7] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.371 ns" { CARRIER_507:inst16|PHASE_WORD[1] CARRIER_507:inst16|Add0~135 CARRIER_507:inst16|Add0~137 CARRIER_507:inst16|Add0~139 CARRIER_507:inst16|Add0~141 CARRIER_507:inst16|Add0~146 CARRIER_507:inst16|PHASE_WORD[7] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.371 ns" { CARRIER_507:inst16|PHASE_WORD[1] {} CARRIER_507:inst16|Add0~135 {} CARRIER_507:inst16|Add0~137 {} CARRIER_507:inst16|Add0~139 {} CARRIER_507:inst16|Add0~141 {} CARRIER_507:inst16|Add0~146 {} CARRIER_507:inst16|PHASE_WORD[7] {} } { 0.000ns 0.807ns 0.000ns 0.000ns 0.000ns 0.000ns 0.708ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.478ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}