?? prev_cmp_fpga_am.tan.qmsg
字號:
{ "Info" "ITDB_FULL_SLACK_RESULT" "LCK register MODEM:inst4\|\\DDS:COUNT\[1\] register MODEM:inst4\|PHASE_WORD\[9\] 13.977 ns " "Info: Slack time is 13.977 ns for clock \"LCK\" between source register \"MODEM:inst4\|\\DDS:COUNT\[1\]\" and destination register \"MODEM:inst4\|PHASE_WORD\[9\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "166.03 MHz 6.023 ns " "Info: Fmax is 166.03 MHz (period= 6.023 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination LCK 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"LCK\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source LCK 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"LCK\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCK destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"LCK\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LCK 1 CLK PIN_17 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 50; CLK Node = 'LCK'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCK } "NODE_NAME" } } { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 120 -520 -352 136 "LCK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns MODEM:inst4\|PHASE_WORD\[9\] 2 REG LC_X15_Y12_N9 4 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y12_N9; Fanout = 4; REG Node = 'MODEM:inst4\|PHASE_WORD\[9\]'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { LCK MODEM:inst4|PHASE_WORD[9] } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[9] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[9] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCK source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"LCK\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LCK 1 CLK PIN_17 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 50; CLK Node = 'LCK'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCK } "NODE_NAME" } } { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 120 -520 -352 136 "LCK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns MODEM:inst4\|\\DDS:COUNT\[1\] 2 REG LC_X17_Y12_N9 3 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y12_N9; Fanout = 3; REG Node = 'MODEM:inst4\|\\DDS:COUNT\[1\]'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { LCK MODEM:inst4|\DDS:COUNT[1] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|\DDS:COUNT[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|\DDS:COUNT[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[9] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[9] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|\DDS:COUNT[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|\DDS:COUNT[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 23 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[9] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[9] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|\DDS:COUNT[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|\DDS:COUNT[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.762 ns - Longest register register " "Info: - Longest register to register delay is 5.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MODEM:inst4\|\\DDS:COUNT\[1\] 1 REG LC_X17_Y12_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y12_N9; Fanout = 3; REG Node = 'MODEM:inst4\|\\DDS:COUNT\[1\]'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { MODEM:inst4|\DDS:COUNT[1] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 1.098 ns MODEM:inst4\|Add0~126COUT1 2 COMB LC_X17_Y12_N1 2 " "Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X17_Y12_N1; Fanout = 2; COMB Node = 'MODEM:inst4\|Add0~126COUT1'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.098 ns" { MODEM:inst4|\DDS:COUNT[1] MODEM:inst4|Add0~126COUT1 } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.178 ns MODEM:inst4\|Add0~128COUT1 3 COMB LC_X17_Y12_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.178 ns; Loc. = LC_X17_Y12_N2; Fanout = 2; COMB Node = 'MODEM:inst4\|Add0~128COUT1'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { MODEM:inst4|Add0~126COUT1 MODEM:inst4|Add0~128COUT1 } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.786 ns MODEM:inst4\|Add0~121 4 COMB LC_X17_Y12_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.608 ns) = 1.786 ns; Loc. = LC_X17_Y12_N3; Fanout = 2; COMB Node = 'MODEM:inst4\|Add0~121'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { MODEM:inst4|Add0~128COUT1 MODEM:inst4|Add0~121 } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.750 ns) + CELL(0.590 ns) 3.126 ns MODEM:inst4\|Equal0~64 5 COMB LC_X16_Y12_N6 3 " "Info: 5: + IC(0.750 ns) + CELL(0.590 ns) = 3.126 ns; Loc. = LC_X16_Y12_N6; Fanout = 3; COMB Node = 'MODEM:inst4\|Equal0~64'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.340 ns" { MODEM:inst4|Add0~121 MODEM:inst4|Equal0~64 } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.590 ns) 4.172 ns MODEM:inst4\|Equal0~66 6 COMB LC_X16_Y12_N2 11 " "Info: 6: + IC(0.456 ns) + CELL(0.590 ns) = 4.172 ns; Loc. = LC_X16_Y12_N2; Fanout = 11; COMB Node = 'MODEM:inst4\|Equal0~66'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.046 ns" { MODEM:inst4|Equal0~64 MODEM:inst4|Equal0~66 } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.867 ns) 5.762 ns MODEM:inst4\|PHASE_WORD\[9\] 7 REG LC_X15_Y12_N9 4 " "Info: 7: + IC(0.723 ns) + CELL(0.867 ns) = 5.762 ns; Loc. = LC_X15_Y12_N9; Fanout = 4; REG Node = 'MODEM:inst4\|PHASE_WORD\[9\]'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { MODEM:inst4|Equal0~66 MODEM:inst4|PHASE_WORD[9] } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.310 ns ( 57.45 % ) " "Info: Total cell delay = 3.310 ns ( 57.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.452 ns ( 42.55 % ) " "Info: Total interconnect delay = 2.452 ns ( 42.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.762 ns" { MODEM:inst4|\DDS:COUNT[1] MODEM:inst4|Add0~126COUT1 MODEM:inst4|Add0~128COUT1 MODEM:inst4|Add0~121 MODEM:inst4|Equal0~64 MODEM:inst4|Equal0~66 MODEM:inst4|PHASE_WORD[9] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.762 ns" { MODEM:inst4|\DDS:COUNT[1] {} MODEM:inst4|Add0~126COUT1 {} MODEM:inst4|Add0~128COUT1 {} MODEM:inst4|Add0~121 {} MODEM:inst4|Equal0~64 {} MODEM:inst4|Equal0~66 {} MODEM:inst4|PHASE_WORD[9] {} } { 0.000ns 0.523ns 0.000ns 0.000ns 0.750ns 0.456ns 0.723ns } { 0.000ns 0.575ns 0.080ns 0.608ns 0.590ns 0.590ns 0.867ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[9] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[9] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|\DDS:COUNT[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|\DDS:COUNT[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.762 ns" { MODEM:inst4|\DDS:COUNT[1] MODEM:inst4|Add0~126COUT1 MODEM:inst4|Add0~128COUT1 MODEM:inst4|Add0~121 MODEM:inst4|Equal0~64 MODEM:inst4|Equal0~66 MODEM:inst4|PHASE_WORD[9] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.762 ns" { MODEM:inst4|\DDS:COUNT[1] {} MODEM:inst4|Add0~126COUT1 {} MODEM:inst4|Add0~128COUT1 {} MODEM:inst4|Add0~121 {} MODEM:inst4|Equal0~64 {} MODEM:inst4|Equal0~66 {} MODEM:inst4|PHASE_WORD[9] {} } { 0.000ns 0.523ns 0.000ns 0.000ns 0.750ns 0.456ns 0.723ns } { 0.000ns 0.575ns 0.080ns 0.608ns 0.590ns 0.590ns 0.867ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0_200M:inst6\|altpll:altpll_component\|_clk0 register CARRIER_507:inst16\|PHASE_WORD\[8\] register CARRIER_507:inst16\|PHASE_WORD\[1\] 1.083 ns " "Info: Minimum slack time is 1.083 ns for clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" between source register \"CARRIER_507:inst16\|PHASE_WORD\[8\]\" and destination register \"CARRIER_507:inst16\|PHASE_WORD\[1\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.874 ns + Shortest register register " "Info: + Shortest register to register delay is 0.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CARRIER_507:inst16\|PHASE_WORD\[8\] 1 REG LC_X15_Y3_N6 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y3_N6; Fanout = 7; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[8\]'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CARRIER_507:inst16|PHASE_WORD[8] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.309 ns) 0.874 ns CARRIER_507:inst16\|PHASE_WORD\[1\] 2 REG LC_X15_Y3_N7 6 " "Info: 2: + IC(0.565 ns) + CELL(0.309 ns) = 0.874 ns; Loc. = LC_X15_Y3_N7; Fanout = 6; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[1\]'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.874 ns" { CARRIER_507:inst16|PHASE_WORD[8] CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 35.35 % ) " "Info: Total cell delay = 0.309 ns ( 35.35 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.565 ns ( 64.65 % ) " "Info: Total interconnect delay = 0.565 ns ( 64.65 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.874 ns" { CARRIER_507:inst16|PHASE_WORD[8] CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.874 ns" { CARRIER_507:inst16|PHASE_WORD[8] {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 0.565ns } { 0.000ns 0.309ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.833 ns " "Info: + Latch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0_200M:inst6\|altpll:altpll_component\|_clk0 5.000 ns -1.833 ns 50 " "Info: Clock period of Destination clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" is 5.000 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0_200M:inst6\|altpll:altpll_component\|_clk0 5.000 ns -1.833 ns 50 " "Info: Clock period of Source clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" is 5.000 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0_200M:inst6\|altpll:altpll_component\|_clk0 destination 2.279 ns + Longest register " "Info: + Longest clock path from clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" to destination register is 2.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0_200M:inst6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 27; CLK Node = 'altpll0_200M:inst6\|altpll:altpll_component\|_clk0'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0_200M:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(0.711 ns) 2.279 ns CARRIER_507:inst16\|PHASE_WORD\[1\] 2 REG LC_X15_Y3_N7 6 " "Info: 2: + IC(1.568 ns) + CELL(0.711 ns) = 2.279 ns; Loc. = LC_X15_Y3_N7; Fanout = 6; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[1\]'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 31.20 % ) " "Info: Total cell delay = 0.711 ns ( 31.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.568 ns ( 68.80 % ) " "Info: Total interconnect delay = 1.568 ns ( 68.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0_200M:inst6\|altpll:altpll_component\|_clk0 source 2.279 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" to source register is 2.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0_200M:inst6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 27; CLK Node = 'altpll0_200M:inst6\|altpll:altpll_component\|_clk0'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0_200M:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(0.711 ns) 2.279 ns CARRIER_507:inst16\|PHASE_WORD\[8\] 2 REG LC_X15_Y3_N6 7 " "Info: 2: + IC(1.568 ns) + CELL(0.711 ns) = 2.279 ns; Loc. = LC_X15_Y3_N6; Fanout = 7; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[8\]'" { } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[8] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 31.20 % ) " "Info: Total cell delay = 0.711 ns ( 31.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.568 ns ( 68.80 % ) " "Info: Total interconnect delay = 1.568 ns ( 68.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[8] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[8] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[8] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.874 ns" { CARRIER_507:inst16|PHASE_WORD[8] CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.874 ns" { CARRIER_507:inst16|PHASE_WORD[8] {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 0.565ns } { 0.000ns 0.309ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[1] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 CARRIER_507:inst16|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { altpll0_200M:inst6|altpll:altpll_component|_clk0 {} CARRIER_507:inst16|PHASE_WORD[8] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
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