{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "LCK register MODEM:inst4\|PHASE_WORD\[8\] register MODEM:inst4\|PHASE_WORD\[8\] 1.323 ns " "Info: Minimum slack time is 1.323 ns for clock \"LCK\" between source register \"MODEM:inst4\|PHASE_WORD\[8\]\" and destination register \"MODEM:inst4\|PHASE_WORD\[8\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.114 ns + Shortest register register " "Info: + Shortest register to register delay is 1.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MODEM:inst4\|PHASE_WORD\[8\] 1 REG LC_X15_Y12_N8 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y12_N8; Fanout = 6; REG Node = 'MODEM:inst4\|PHASE_WORD\[8\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.507 ns) + CELL(0.607 ns) 1.114 ns MODEM:inst4\|PHASE_WORD\[8\] 2 REG LC_X15_Y12_N8 6 " "Info: 2: + IC(0.507 ns) + CELL(0.607 ns) = 1.114 ns; Loc. = LC_X15_Y12_N8; Fanout = 6; REG Node = 'MODEM:inst4\|PHASE_WORD\[8\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { MODEM:inst4|PHASE_WORD[8] MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 54.49 % ) " "Info: Total cell delay = 0.607 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.507 ns ( 45.51 % ) " "Info: Total interconnect delay = 0.507 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { MODEM:inst4|PHASE_WORD[8] MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.114 ns" { MODEM:inst4|PHASE_WORD[8] {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.507ns } { 0.000ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination LCK 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"LCK\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source LCK 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"LCK\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCK destination 2.782 ns + Longest register " "Info: + Longest clock path from clock \"LCK\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LCK 1 CLK PIN_17 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 50; CLK Node = 'LCK'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCK } "NODE_NAME" } } { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 120 -520 -352 136 "LCK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns MODEM:inst4\|PHASE_WORD\[8\] 2 REG LC_X15_Y12_N8 6 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y12_N8; Fanout = 6; REG Node = 'MODEM:inst4\|PHASE_WORD\[8\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCK source 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"LCK\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LCK 1 CLK PIN_17 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 50; CLK Node = 'LCK'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCK } "NODE_NAME" } } { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 120 -520 -352 136 "LCK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns MODEM:inst4\|PHASE_WORD\[8\] 2 REG LC_X15_Y12_N8 6 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y12_N8; Fanout = 6; REG Node = 'MODEM:inst4\|PHASE_WORD\[8\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { MODEM:inst4|PHASE_WORD[8] MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.114 ns" { MODEM:inst4|PHASE_WORD[8] {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.507ns } { 0.000ns 0.607ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { LCK MODEM:inst4|PHASE_WORD[8] } "NODE_NAME" } } { "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "i:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { LCK {} LCK~out0 {} MODEM:inst4|PHASE_WORD[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "MODEM:inst4\|PHASE_WORD\[5\] fsk_data LCK 5.729 ns register " "Info: tsu for register \"MODEM:inst4\|PHASE_WORD\[5\]\" (data pin = \"fsk_data\", clock pin = \"LCK\") is 5.729 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.474 ns + Longest pin register " "Info: + Longest pin to register delay is 8.474 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns fsk_data 1 PIN PIN_122 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 5; PIN Node = 'fsk_data'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingCl