{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 27 15:42:31 2008 " "Info: Processing started: Wed Aug 27 15:42:31 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FPGA_AM -c FPGA_AM " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FPGA_AM -c FPGA_AM" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "source/CARRIER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file source/CARRIER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CARRIER-BUILDING " "Info: Found design unit 1: CARRIER-BUILDING" {  } { { "source/CARRIER.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CARRIER " "Info: Found entity 1: CARRIER" {  } { { "source/CARRIER.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "source/MODEM.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file source/MODEM.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MODEM-BUILDING " "Info: Found design unit 1: MODEM-BUILDING" {  } { { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 MODEM " "Info: Found entity 1: MODEM" {  } { { "source/MODEM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/MODEM.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BU_MA.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file BU_MA.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BU_MA-BUILDING " "Info: Found design unit 1: BU_MA-BUILDING" {  } { { "BU_MA.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/BU_MA.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 BU_MA " "Info: Found entity 1: BU_MA" {  } { { "BU_MA.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/BU_MA.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "source/FPGA_AM_TEST.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file source/FPGA_AM_TEST.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FPGA_AM_TEST " "Info: Found entity 1: FPGA_AM_TEST" {  } { { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "source/test.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file source/test.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TEST-BUILDING " "Info: Found design unit 1: TEST-BUILDING" {  } { { "source/test.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/test.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 TEST " "Info: Found entity 1: TEST" {  } { { "source/test.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/test.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "source/CARRIER_KHZ507.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file source/CARRIER_KHZ507.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CARRIER_507-BUILDING " "Info: Found design unit 1: CARRIER_507-BUILDING" {  } { { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CARRIER_507 " "Info: Found entity 1: CARRIER_507" {  } { { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FPGA_AM_TEST " "Info: Elaborating entity \"FPGA_AM_TEST\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "lAM_FUDU inst10 " "Warning: Block or symbol \"lAM_FUDU\" of instance \"inst10\" overlaps another block or symbol" {  } { { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 352 48 216 448 "inst10" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "ADD256 inst12 " "Warning: Block or symbol \"ADD256\" of instance \"inst12\" overlaps another block or symbol" {  } { { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 352 272 432 448 "inst12" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "FI_OUT.vhd 2 1 " "Warning: Using design file FI_OUT.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fi_out-SYN " "Info: Found design unit 1: fi_out-SYN" {  } { { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 FI_OUT " "Info: Found entity 1: FI_OUT" {  } { { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FI_OUT FI_OUT:inst15 " "Info: Elaborating entity \"FI_OUT\" for hierarchy \"FI_OUT:inst15\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst15" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 312 736 896 408 "inst15" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "FI_OUT.vhd" "lpm_add_sub_component" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i:/altera/72/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i:/altera/72/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 76 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder " "Info: Elaborating entity \"addcore\" for hierarchy \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\"" {  } { { "lpm_add_sub.tdf" "adder" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\", which is child of megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 10 " "Info: Parameter \"lpm_width\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:oflow_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:oflow_node\"" {  } { { "addcore.tdf" "oflow_node" { Text "i:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:oflow_node FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "addcore.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 10 " "Info: Parameter \"lpm_width\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "i:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "addcore.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 10 " "Info: Parameter \"lpm_width\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}