{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i:/altera/72/quartus/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i:/altera/72/quartus/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altshift.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|altshift:result_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|altshift:result_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "result_ext_latency_ffs" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|altshift:result_ext_latency_ffs FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 10 " "Info: Parameter \"lpm_width\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|altshift:carry_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|altshift:carry_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "carry_ext_latency_ffs" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|altshift:carry_ext_latency_ffs FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"FI_OUT:inst15\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 10 " "Info: Parameter \"lpm_width\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "FI_OUT.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/FI_OUT.vhd" 78 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "AM_MOD.vhd 2 1 " "Warning: Using design file AM_MOD.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 am_mod-SYN " "Info: Found design unit 1: am_mod-SYN" {  } { { "AM_MOD.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/AM_MOD.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 AM_MOD " "Info: Found entity 1: AM_MOD" {  } { { "AM_MOD.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/AM_MOD.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AM_MOD AM_MOD:inst14 " "Info: Elaborating entity \"AM_MOD\" for hierarchy \"AM_MOD:inst14\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst14" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 296 536 704 392 "inst14" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" 284 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult AM_MOD:inst14\|lpm_mult:lpm_mult_component " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"AM_MOD:inst14\|lpm_mult:lpm_mult_component\"" {  } { { "AM_MOD.vhd" "lpm_mult_component" { Text "J:/FPGA/my_exercises/AM/project/AM_MOD.vhd" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "AM_MOD:inst14\|lpm_mult:lpm_mult_component " "Info: Elaborated megafunction instantiation \"AM_MOD:inst14\|lpm_mult:lpm_mult_component\"" {  } { { "AM_MOD.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/AM_MOD.vhd" 77 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_1sm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_1sm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_1sm " "Info: Found entity 1: mult_1sm" {  } { { "db/mult_1sm.tdf" "" { Text "J:/FPGA/my_exercises/AM/project/db/mult_1sm.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_1sm AM_MOD:inst14\|lpm_mult:lpm_mult_component\|mult_1sm:auto_generated " "Info: Elaborating entity \"mult_1sm\" for hierarchy \"AM_MOD:inst14\|lpm_mult:lpm_mult_component\|mult_1sm:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BU_MA BU_MA:inst " "Info: Elaborating entity \"BU_MA\" for hierarchy \"BU_MA:inst\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 272 144 352 368 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "TEMP_DATA_OUT BU_MA.vhd(15) " "Warning (10631): VHDL Process Statement warning at BU_MA.vhd(15): inferring latch(es) for signal or variable \"TEMP_DATA_OUT\", which holds its previous value in one or more paths through the process" {  } { { "BU_MA.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/BU_MA.vhd" 15 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom0_394.vhd 2 1 " "Warning: Using design file lpm_rom0_394.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom0_394-SYN " "Info: Found design unit 1: lpm_rom0_394-SYN" {  } { { "lpm_rom0_394.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/lpm_rom0_394.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0_394 " "Info: Found entity 1: lpm_rom0_394" {  } { { "lpm_rom0_394.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/lpm_rom0_394.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0_394 lpm_rom0_394:inst9 " "Info: Elaborating entity \"lpm_rom0_394\" for hierarchy \"lpm_rom0_394:inst9\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst9" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 96 208 368 176 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0_394:inst9\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0_394:inst9\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0_394.vhd" "altsyncram_component" { Text "J:/FPGA/my_exercises/AM/project/lpm_rom0_394.vhd" 84 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0_394:inst9\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_rom0_394:inst9\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0_394.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/lpm_rom0_394.vhd" 84 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_rom0_394_altsyncram.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_rom0_394_altsyncram.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0_394_altsyncram " "Info: Found entity 1: lpm_rom0_394_altsyncram" {  } { { "db/lpm_rom0_394_altsyncram.v" "" { Text "J:/FPGA/my_exercises/AM/project/db/lpm_rom0_394_altsyncram.v" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0_394_altsyncram lpm_rom0_394:inst9\|altsyncram:altsyncram_component\|lpm_rom0_394_altsyncram:auto_generated " "Info: Elaborating entity \"lpm_rom0_394_altsyncram\" for hierarchy \"lpm_rom0_394:inst9\|altsyncram:altsyncram_component\|lpm_rom0_394_altsyncram:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "i:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "altpll0_200M.vhd 2 1 " "Warning: Using design file altpll0_200M.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altpll0_200m-SYN " "Info: Found design unit 1: altpll0_200m-SYN" {  } { { "altpll0_200M.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/altpll0_200M.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 altpll0_200M " "Info: Found entity 1: altpll0_200M" {  } { { "altpll0_200M.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/altpll0_200M.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll0_200M altpll0_200M:inst6 " "Info: Elaborating entity \"altpll0_200M\" for hierarchy \"altpll0_200M:inst6\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst6" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 64 -312 -72 224 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i:/altera/72/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i:/altera/72/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 476 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll0_200M:inst6\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"altpll0_200M:inst6\|altpll:altpll_component\"" {  } { { "altpll0_200M.vhd" "altpll_component" { Text "J:/FPGA/my_exercises/AM/project/altpll0_200M.vhd" 129 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altpll0_200M:inst6\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"altpll0_200M:inst6\|altpll:altpll_component\"" {  } { { "altpll0_200M.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/altpll0_200M.vhd" 129 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}