?? frequency1hz.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity frequency1hz is
port(clk :in std_logic;
clk1khz : out std_logic);
end entity;
architecture beha of frequency1hz is
signal count : integer range 0 to 499;
signal z : std_logic:='0';
begin
process(clk)
begin
if(clk'event and clk='1')then
if (count=499) then
z<= not z;
count<=0;
else
count<=count+1;
end if;
end if;
end process;
clk1khz<=z;
end architecture ;
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