?? fenwei.tan.qmsg
字號:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 14 17:12:38 2008 " "Info: Processing started: Fri Nov 14 17:12:38 2008" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off fenwei -c fenwei --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fenwei -c fenwei --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 6 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
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